Senior Design Verification Engineer - Hyderabad, India - Kaizen

Description

• 5 Years Experience As a Design Verification Engineer
• Experience in IP/Subsystem/SOC ASIC Verification.
• Hands-on expertise in working on Test Plans and test bench development.
• Expertise in writing test cases, simulation and debugging.
• Experience building a Verification Environment from scratch using System-Verilog and methodologies like UVM / OVM.
• Experience in developing Test Plans and Test Cases
• Expertise in Coverage verification, Function coverage & Code coverage analysis
• Hands-on work experience on any of PCIe/Eth/USB/DDR/AXI etc.)