Arun Kumar Madupathi

I am Arun Kumar Madupathi, a Design & Verification trainee at VLSI FIRST, Hyderabad, with hands-on skills in RTL design, Verilog, SystemVerilog, and Cadence Virtuoso. Currently pursuing B.Tech in ECE, I am passionate about semiconductor design and verification.

Currently working as a Design & Verification Trainee at VLSI FIRST, Hyderabad (June 2025 – Present). I am gaining hands-on experience in RTL design, Verilog, SystemVerilog, and digital electronics, with exposure to semiconductor tools such as Cadence Virtuoso,Questa sim,Quartus.

B.Tech in Electronics and Communication Engineering (2021 – 2025) at Marri Laxman Reddy Institute of Technology and Management, Telangana. My course work includes VLSI design, digital electronics, and semiconductor fundamentals.