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Chennai
Kishore S

Kishore S

RTL & FPGA Design |SoC, DFT & ATPG |NoC Enthusiast

Engineering / Architecture

Chennai, Chennai district

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About Kishore S:

I’m a final-year Electronics and Communication Engineering (ECE) student with a strong passion for VLSI system design and digital hardware architecture. I specialize in RTL design using Verilog, FPGA-based prototyping, and SoC-level integration. My core interests include Network-on-Chip (NoC), Design for Testability (DFT), and Automatic Test Pattern Generation (ATPG). I enjoy bridging the gap between hardware and software through embedded system development and custom RTL implementations.

I’m actively exploring opportunities where I can contribute to advanced semiconductor and VLSI design, defense electronics, or 5G/AI-enabled architectures using FPGAs and custom NoC designs. I’m proficient with tools and platforms like Vivado, Vitis, and Xilinx Versal ACAP.

In addition to my core electronics expertise, I’ve completed the CCNA certification and have working knowledge of scripting languages like Python and C, which I use to support test automation and system validation.

Experience

Final-year Electronics and Communication Engineering student with hands-on experience in RTL design using Verilog, FPGA prototyping, and SoC-level integration. Skilled in VLSI concepts including DFT, ATPG, and NoC-based system architecture. Proficient with industry-standard tools like Vivado, Vitis, and Xilinx Versal ACAP. Also knowledgeable in scripting with Python and C for test automation and embedded development. Completed CCNA certification, supporting foundational understanding of networking in system-level design. Passionate about building scalable hardware systems for semiconductor, defense, and 5G/AI applications.

Education

Pursuing a Bachelor of Engineering (B.E.) in Electronics and Communication Engineering with a strong academic focus on VLSI design, digital system architecture, and embedded systems. Coursework and projects emphasize RTL design (Verilog), FPGA prototyping, SoC and NoC integration, and Design for Testability (DFT) techniques including ATPG. Supplemented academic learning with certifications like CCNA and scripting in Python and C to support system-level design and automation.

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