Manish Patil

Working with Cross-functional teams to ensure design quality and help teams to be aligned and productive.

Involved in and Responsible for specification discussion till post-silicon validation and sign-offs.

Knowledge of complete ASIC flow. 

In my complete experience of more than 15 years in Semiconductor industry, I worked in Custom analog design for more than 10years, and now since last almost 5 years working as a IP design lead.

Very good team player, responsible Lead, with innovative ideas to improve design execution helping my Company to identify bugs early and avoid any last minute design/specs issues.

Presently working on DDR phy design.

In past, worked on MIPI D-PHY, Viewpin, Die2Die IPs as a Circuit design engineer and IP Lead.

Master of Engineering from SSGMCE, one of the well-known engineering college of Maharashtra.