priyanka velugubantla

• Accredited Physical Design Engineering Expert offering over 4.9 years of rich experience specialising in Semiconductor Design, Timing Analysis & Closure, Floor Planning, and Flow Development with a solid background in AMD-ODC, Synopsys-ODC environments, requirements gathering & analysis, & quality assurance within the Semiconductor Manufacturing sector
• Leverages expertise in implementing physical design from Netlist to GDS with an adequate understanding of scripting using Perl, TCL, C Shell, & Python basics, and optimizing the timing sign-off criteria, timing analysis methodologies, flow, & enhancing auto ECO generation scripts for timing closures, and also efficient in Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
• Adroit in staying abreast of emerging technologies & nodes, including 22nm, 10nm, & 7nm and possessing hands-on experience in managing multiple timing/congestion critical blocks with high instance-count/frequency and ensuring the compliance of various industry standards, including CAD methodologies from Cadence (Encounter, Innovus, Voltus, & Tempus), Synopsys (ICC2, DC, PT, star RC), Ansys (Redhawk) and Mentor Graphics (Calibre, Calibre PERC)
• Adept at manoeuvring back-end implementation from RTL to GDS2, including synthesis, FV, floor-planning, net listing, timing constraints, timing & power convergence, and ECO implementation with a keen focus on high-speed memory systems design like DDR3, LPDDR3, and LPDDR4 IP
• Dexterous technocrat possessing an in-depth knowledge of CMOS digital logic designing concepts, logic verification, low-power chip implementation, developing codes, planning clocking network & analysis, ESD (Electrostatic Discharge) using PERC
• Profound efficiency in integrating multi-voltage block with island-based floor-plan design & support, automatic placement & routing with multi-criteria optimization, and correlating with cross-functional teams with the ability to develop models from conceptual designs/inputs within timelines, and ensuring smooth project execution & on-time delivery at all times

 Leveraging expertise in streamlining the timing sign-off criterion's, timing analysis methodologies and flows and developing/enhancing auto ECO generation scripts for timing closure  Gained expertise on all stages of PnR (Floor Planning, Placement, Clock Tree Synthesis, Routing, Timing Closure and ECO)  Experienced in advanced technology nodes such as 22nm, 10nm and 7nm; skilled in managing multiple timing/congestion critical blocks with high inst-count/frequency  Gained knowledge in working with industry standard CAD methodologies from Cadence (Encounter, Innovus, Voltus, Tempus), Synopsys (ICC2, DC, PT, star RC), Ansys (Redhawk) and Mentor Graphics (Calibre, Calibre PERC)  Proficiency in driving back-end implementation from RTL to GDS2, including synthesis, FV, floor-planning, netlisting, timing constraints, timing and power convergence, and ECO implementation  Exposure in high speed memory system design, including DDR3, LPDDR3 and LPDDR4 IP designing projects and acted as a part of on-time deliverable s and tape outs  Gained rich knowledge on CMOS digital logic designing concepts and expertise in logic verification and low power chip implementation (including UPF) and multiple clock domains management  Excellence in developing codes, as well as planning clocking network and analysis; experienced in ESD (Electro static Discharge) circuit analysis using PERC

Bachelor of Engineering in Electronics & Communication Engineering, Jawaharlal Nehru Technological University,(2014-2018) Kakinada, Andhra Pradesh, India