
Shivanand S Pasar
Education / Training
About Shivanand S Pasar:
Aspiring Physical Design Engineer with hands-on experience in 40nm technology,
layout design, and Automated Place and Route (APR) optimization. Passionate
about leveraging technical expertise and problem-solving skills to contribute to
cutting-edge semiconductor designs and enhance performance and efficiency.
Eager to join a dynamic team and grow within the semiconductor industry.
Experience
- Entry-level Physical Design Engineer with industrial training experience in the
semiconductor industry focused on digital and analog circuit design. - Skilled in using industry-standard EDA tools, including Synopsys IC Compiler II,
for place-and-route (P&R), and Primetime for Static Timing Analysis (Timing
Closer). - Proficient in physical design workflows such as floor planning, power planning,
placement, clock tree synthesis (CTS), routing, and signoffs. - Hands-on experience with 40nm technology and understanding of design rule
checking (DRC), and layout-versus-schematic (LVS) processes, IR Drop analysis,
Placement Congestion. - Completed specialized coursework and training programs in VLSI design,
semiconductor fabrication, and ASIC development methodologies. - Demonstrates problem-solving skills, attention to detail, and effective
communication in collaborating with teams to achieve project goals. - Eager to contribute technical expertise and grow within a dynamic team to
develop innovative semiconductor products.
Education
Advanced Diploma in ASIC Design
RV-VLSI Design Center Bengaluru
Bachelor of Technology in Electronics and Communications Engineering
M S Ramaiah University of Applied Science, Bengaluru
First Class
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