About Vishal Pattanad:
Design Verification Engineer with 2 years of experience. Worked on protocols like Ethernet, AMBA AHB, CPRI.
Experience
Skilled in Verilog, System Verilog, UVM methodology. Have knowledge in Digital Logic design. Good Knowledge on constraint randomization
Education
Graduated M.Tech in 2020, specialized in VLSI Design and Embedded Systems.
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