beBeeSTA Jobs in India

Senior Timing Analyst Job Description · As a Senior Timing Analyst, you will play a crucial role in ensuring the timely completion of complex projects in our dynamic environment. · You will be responsible for developing and implementing timing analysis strategies to optimize proj ...

Static Timing Analysis Engineer Job Description · We are seeking a skilled Static Timing Analysis engineer to join our team. · Perform comprehensive block-level and full-chip STA analysis with attention to detail and a focus on quality. · ...

Static Timing Analysis Specialist · We are seeking a seasoned Static Timing Analysis expert to join our team. · Create, refine and validate SDC constraints including clocks, generated clocks, false paths and multi-cycle paths. · Drive tuning closure during synthesis place & route ...

Static Timing Analysis Expert · We are seeking experts to perform Static Timing Analysis on full-chip designs. · Responsibilities: · <ol type= ...

Key Role: Lead STA Engineer · The selected candidate will be responsible for performing in-depth Static Timing Analysis (STA) to ensure the timely completion of projects. · Bulk analysis and full-chip Static Timing Analysis (STA) · Developing, implementing and maintaining SDC tim ...

About STA Engineer Role · This role is responsible for performing static timing analysis (STA) at the block and full-chip levels. · STA Analysis: Perform block-level and full-chip Static Timing Analysis to ensure compliance with design specifications. · SandyBridge SDC Management ...

STA Engineer · We are seeking a seasoned STA professional to spearhead our team in Bangalore. · The ideal candidate will oversee block-level and full-chip Static Timing Analysis (STA), develop and maintain SDC timing constraints, collaborate with PD, CTS, and Design teams for tim ...

STA Engineer Role Overview · We are seeking an experienced STA (Static Timing Analysis) engineer to join our team. The ideal candidate will have a strong background in performing block-level static timing analysis, developing SDC timing constraints, and collaborating with PD team ...

Complex SoC block implementation and full-chip designs require a high level of expertise in RTL-to-GDSII targeting performance, power, and area (PPA) optimization. · About the role: · This engineer will be responsible for implementing complex SoC blocks or full-chip designs with ...