BITSILICA Jobs in India

We are looking for a Physical Design Manager with 12+ years of experience in the entire PD process from Netlist to GDS Generation. · Proven experience in Synthesis, PnR, STA, and Timing Closure · ...

We are looking for a skilled SoC design verification engineer with strong experience in systemVerilog and uvm. · ...

Responsibilities · - 4+ years experience in semiconductor industry · - Hands-on experience with System Verilog as High-level Verification Language and UVM implementation. · - Debugging digital simulation in both RTL and gate-level netlist, isolating issues in both module and syst ...

Job Description · We are looking for an experienced IP Verification Engineer. · 4+ years of experience in the semiconductor industry. · Familiarity with System Verilog as a High-level Verification Language and UVM implementation. · ...

As an experienced candidate with 5+ years of experience. · ...

We are looking for seasoned Design Verification (DV) Engineers and Lead Architects to join our team in Bengaluru and Hyderabad. You will be responsible for the end-to-end verification of high-speed IPs and complex SoCs. · ...

+4 years experience in semiconductor industry · Hands-on experience with System Verilog as High-level Verification Language and UVM implementation. · Job summary: · A position requiring verification expertise in semiconductor industry. ...

We are looking for a skilled SoC Design Verification Engineer with strong experience in SystemVerilog and UVM. · Key Responsibilities:SoC/IP/Subsystem verification using SV-UVM. · Develop verification plans, test benches, and test cases. · ...

We are looking for a skilled SoC & GLS Verification Engineer to join our growing team at BITSILICA. · Perform SoC & GLS Verification · Utilize SystemVerilog UVM C for verification tasks · Have a good understanding of AMBA protocols such as AXI AHB APB · ...

Develop comprehensive verification plans and strategies for SoC and GLS components. · ...

We are looking for an experienced Verification Engineer to join our team. The successful candidate will have a strong background in System Verilog and UVM implementation. · ...

Develop comprehensive verification plans and strategies for SoC and GLS components. · Design, implement, and maintain reusable testbenches using SystemVerilog methodologies. · ...

+We need a Physical Design Manager with 12+ years of experience in the entire PD process from Netlist to GDS Generation. · +Proven experience in Synthesis, PnR, STA, and Timing Closure · Familiarity with Synopsys / Cadence / Mentor tool flows · ...

The job is for an IP Verification Engineer in the semiconductor industry. · ...