Faststream Technologies Jobs in India

We are looking for experienced Physical Design Engineers with strong expertise in high-speed, ultra-wide memory interface implementation. · ...

Senior RTL Integration Engineer · We are looking for a senior engineer to integrate complex SoC and chiplet subsystems involving high-speed interfaces. · Integrate complex RTL subsystems into SoC / chiplet top level · Work with PCIe Gen4/5/6, Ethernet 100G / 200G / 224G multi-rat ...

Key Responsibilities · Physical Design & Floorplanning: · Lead and execute floorplanning for large SRAM-based memory subsystems. · Plan and implement ultra-wide high-speed data interfaces (~2K-bit wide SRAM interfaces). · ...

Job Description · We are looking for a senior RTL Integration Engineer to integrate and deliver complex SoC and chiplet subsystems involving high-speed interfaces such as PCIe, Ethernet, , and SerDes. The role requires close collaboration with architecture, DV, analog/SerDes, fir ...

Summary · The Role of Physical Design Engineer · We seek an experienced Physical Design Engineer with expertise in high-speed memory interface implementation. · Strong hands-on experience working with advanced technology nodes, preferably below 7nm, · Deep understanding of timing ...

Key Responsibilities · Physical Design & Floorplanning · Lead and execute floorplanning for large SRAM-based memory subsystems. · Plan and implement ultra-wide high-speed data interfaces (~2K-bit wide SRAM interfaces). · , · ,Perform congestion analysis and optimize floorplan for ...

We are looking for a senior RTL Integration Engineer to integrate and deliver complex SoC and chiplet subsystems involving high-speed interfaces such as PCIe, · •Pcie (Gen4/5/6), · • Ethernet (100G / 200G / 224G multi-rate), DDR4 / DDR5. · <div dir= ...

Job Description · We are looking for a senior RTL Integration Engineer to integrate and deliver complex SoC and chiplet subsystems involving high-speed interfaces such as PCIe, Ethernet, DDR, and SerDes. · Integrate complex RTL subsystems and IPs into SoC / chiplet top level · Wo ...

Role Overview · We are seeking experienced Physical Design Engineers with expertise in high-speed memory interface implementation for large-scale SRAM-based subsystems used in next-generation SoCs. · Plan and implement ultra-wide data interfaces (~2000-bit wide) using advanced te ...

Job Description · We seek experienced Physical Design Engineers with strong expertise in implementing high-speed, ultra-wide memory interfaces. · This role involves planning floorplanning timing closure and simultaneous read/write optimization for large-scale SRAM-based memory su ...

Key Responsibilities · Lead and execute floorplanning for large SRAM-based memory subsystems. · Plan and implement ultra-wide high-speed data interfaces (~2K-bit wide SRAM interfaces). · SUPPORT INTEGRATION OF LARGE MEMORY ARRAYS CONSISTING OF MULTI-MODULE CONFIGURATIONS (e.g., 5 ...

Job Description · At Faststream Technologies, we're looking for experienced Physical Design Engineers with expertise in implementing high-speed memory interfaces. · Plan floorplanning for large SRAM-based memory subsystems. · Implement ultra-wide high-speed data interfaces (~2K-b ...

We are looking for a senior RTL Integration Engineer to integrate and deliver complex SoC and chiplet subsystems involving high-speed interfaces such as PCIe, Ethernet, DDR, · SerDes. The role requires close collaboration with architecture, · DV, · analog/SerDes, · firmware, · an ...

Job Overview · We seek experienced Physical Design Engineers with expertise in high-speed, ultra-wide memory interface implementation. · The role involves planning, floorplanning, timing closure, and simultaneous read/write optimization for large-scale SRAM-based memory subsystem ...

Job Description · We are seeking a skilled Physical Design Engineer with expertise in implementing high-speed, ultra-wide memory interfaces. · The ideal candidate will have hands-on experience working with advanced technology nodes (7nm or below) and a deep understanding of timin ...

Key Responsibilities · Physical Design & Floorplanning: · <ol type= ...

Senior RTL Integration Engineer · We are looking for a senior RTL Integration Engineer to integrate and deliver complex SoC and chiplet subsystems involving high-speed interfaces such as PCIe, Ethernet, DDR, and SerDes. · Integrate complex RTL subsystems and IPs into SoC / chiple ...

Job Summary · We are seeking a skilled Senior RTL Integration Engineer with extensive knowledge of high-speed interfaces such as PCIe Gen4/5/6 Ethernet multi-rate DDR4 DDR5 SerDes third-party IPs Synopsys Cadence integration clocking reset power domains interconnects AXI NoC Syst ...

Senior RTL Integration Engineer · We seek an experienced Senior RTL Integration Engineer to lead complex SoC/subsystem integrations involving high-speed interfaces such as PCIe, Ethernet, DDR4/DDRS5 and SerDes. · Integrate third-party IPs (Synopsys/Cadence/in-house) · Handle cloc ...

Senior RTL Integration Engineer · We are looking for a senior RTL Integration Engineer to integrate and deliver complex SoC and chiplet subsystems involving high-speed interfaces such as PCIe, Ethernet, DDR, and SerDes. · The role requires close collaboration with architecture, D ...