Sintegra Inc. Jobs in India

Job summaryHands-on experience in ASIC timing constraints generation and timing closure · Expertise and advanced knowledge of industry standard timing EDA tools (Tempus preferred) · Deep understanding and experience in timing closure of various functional and test modes · Experti ...

We are seeking experienced engineers to close subsystems and designs. Key requirements include: · Hands-on experience in generating ASIC timing constraints and achieving timing closure. · Advanced knowledge of industry-standard timing EDA tools, particularly Tempus. · Deep unders ...

We are seeking a skilled and motivated Design Verification Engineer (DV) with expertise in Ethernet protocols, MAC layer functionality, RoCE (RDMA over Converged Ethernet), Synopsys Ethernet PHY and controller IPs. The ideal candidate will have hands-on experience with these tec ...

We are looking for engineers with experience closing subsystems and larger designs. · ...

We are seeking a skilled and motivated Design Verification Engineer (DV) with expertise in Ethernet protocols, · Develop and execute verification plans for Ethernet MAC and PHY IP blocks. · ...

Job Description · We are seeking a skilled Design Verification Engineer with expertise in Ethernet protocols, MAC layer functionality, and RoCE (RDMA over Converged Ethernet). · The ideal candidate will have hands-on experience with Synopsys Ethernet PHY and controller IPs. · ...

We are looking for STA Engineers · Job Requirements · Closure of subsystems and larger designs with hands-on experience in ASIC timing constraints generation. · Detailed knowledge of industry-standard EDA tools, preferably Tempus, along with scripting languages like csh/bash, TCL ...

We are looking for engineers with experience closing subsystems and larger designs. · Hands-on experience in ASIC timing constraints generation and timing closureExpertise and advanced knowledge of industry standard timing EDA tools (Tempus preferred)Deep understanding and experi ...

We are seeking a skilled and motivated · Design Verification Engineer (DV) · , with expertise in Ethernet protocols, · MAC layer functionality, · RoCE (RDMA over Converged Ethernet) Key Responsibilities · Develop and execute verification plans for Ethernet MAC and PHY IP blocks · ...

We are seeking experienced engineers to close subsystems and larger designs. The requirements include: · Hands-on experience in generating ASIC timing constraints and achieving timing closure · Expertise in industry standard EDA tools such as Tempus, with advanced knowledge · Dee ...

STA Engineer · This role involves closing subsystems and larger designs using advanced knowledge of industry-standard EDA tools like Tempus. · Hands-on experience in generating ASIC timing constraints. · Tech Requirements · Expertise in industry standard timing EDA tools (Tempus ...

Job Description · We seek a skilled Design Verification Engineer with hands-on experience in Synopsys Ethernet PHY and controller IPs. · Develop verification plans for Ethernet IP blocks · Implement testbenches using UVM methodology · ...

Design Verification Engineer · We are seeking a skilled and motivated Design Verification Engineer (DV) with expertise in Ethernet protocols, MAC layer functionality, and RoCE. · Develop and execute verification plans for Ethernet MAC and PHY IP blocksValidate RoCE protocol imple ...