Tecquire Solutions Jobs in India

Job Title: Analog Layout Engineer · We are seeking a skilled Analog / Mixed-Signal Layout Engineer to drive full-custom layout implementation at both block and top levels for advanced-node silicon programs. · Design and develop full-custom analog/mixed-signal layouts at block and ...

Design and develop analog and mixed-signal circuits such as amplifiers, comparators, ADCs/DACs, LDOs, and voltage/current references. · Perform schematic design · Transistor-level simulation · ...

Work independently on SRAM memory IP layout development. · ...

Design and develop analog circuits. · Perform schematic design, transistor-level simulation, and layout review. · ...

Design Verification Engineer. · Turing RTL and GLS functional and Low Power subsystem verification . Owning of regression blocks verification . Interact with Design team and cross-functional teams to get task done.Turing subsystem verification. · Handle subsystem verification , r ...

Title: Analog Layout Engineer · Location: Bangalore (On-site) | WFO - 5 Days | 2 - 7 Yrs of Experience · Job Description · We are looking for a highly skilled Analog / Mixed-Signal Layout Engineer to drive full-custom layout implementation at both block and top levels for advance ...

Title: Analog Layout Engineer · Location: Bangalore (On-site) | WFO - 5 Days | 2 - 7 Yrs of Experience · Job Description · We are looking for a highly skilled Analog / Mixed-Signal Layout Engineer to drive full-custom layout implementation at both block and top levels for advance ...

Design analog and mixed-signal circuits such as amplifiers comparators ADCs DACs LDOs voltage current references. · ...

Expert in either of Power Management or Data Converter designs.Expertise includes implementation of various Analog functions and experience in designing precision analog circuits like operational amplifiers,Bandgap,POR,LDOs,Filters,VGA,comparators and oscillators. · Candidate mus ...

Turing RTL and GLS verification. · Verify subsystems of Turing design. ...

Develops memory IP layout designs for SRAM. · Proficient with calibre LVS/DRC verification. Leafcell development of leafcell · ...