- Work experience with node 7nm or lower node designs with advanced low power techniques is must.
- Experience on ASIC Physical Design : Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, Physical Verification are essential part of the job.
- Well versed with Cadence or Synopsys tools is important.
- Experience with Static Timing Analysis in Primetime or Primetime-SI is important.
- Handson experience in scripting languages such as PERL, TCL is important.
- Timing closure on highspeed interfaces is a plus.
- Knowledge on Full chip Physical Design is beneficial.
- Good ASIC fundamentals and problemsolving skills is preferred.
- Experience with 7nm node.
- Experience with Cadence Innovus
-
Sykatiya Technologies
20 hours ago
Sykatiya Technology Pvt Ltd Bangalore/Hyderabad, India permanentRoles & Responsibilities : · 1. You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites. · 2. Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM method ...
Sykatiya Technologies - hyderabad, India - Sykatiya Technology Pvt Ltd
Description
Roles and Responsibilities :