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- Perform Sub system level floor planning, placement, and routing for highperformance microprocessor design.
- Collaborate with crossfunctional teams to achieve design goals.
- Close the design to meet timing, power, and area requirements.
- Implement engineering change orders (ECOs) to rectify functional bugs and timing issues.
- Ensure the quality and efficiency of the RTL to GDS2 implementation process.
- 12+ years of industry experience
- Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure.
- Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration .
- Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints .
- Should have experience in handling asynchronous timing, multiple corner timing closure.
- Preferred Technical and Professional Experience
- Automation skills in PERL ,SKILL and/or TCL
- Preferred EducationMaster's Degree)
Senior Physical Design Engineer - Bangalore, India - ConnectPro Management Consultants Pvt Ltd.
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