Frontend Technical Lead - Bangalore Metropolitan Area, India - Mulya Technologies
Description
Fortune 500 Organization
location: bangalore
Job Overview: As a Frontend Technical Manager specializing in Semiconductor Chip Design, you will lead and coordinate the execution of the front-end stages of integrated circuit development. This role requires a strong technical background in digital design, verification, synthesis, power management, DFT, and exceptional project management skills. Additionally, you will oversee product support activities for both Pre-production and Post-production stages, ensuring the successful initiation, development, and sustainment of semiconductor designs.
Key Responsibilities:
1.Project Planning and Execution: Develop and maintain project plans, timelines, and milestones for front-end design phases of chip design. Coordinate with engineering teams to ensure project goals are clearly defined and aligned with overall business objectives. Monitor and manage project progress, identifying potential risks and implementing mitigation strategies.
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2.Verification Planning and Management: Develop a robust verification strategy and plan for the digital design, ensuring comprehensive coverage of functional and performance requirements. Manage the execution of verification plans, including the creation and execution of effective testbenches and methodologies. Oversee the development and implementation of verification environments, ensuring thorough and efficient verification of digital designs.
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3.Stakeholder Communication: Communicate project status, risks, and milestones to internal and external stakeholders.
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4.Documentation: Maintain accurate and up-to-date project documentation, including design specifications, test plans, and progress reports. Ensure compliance with industry standards and regulations.
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5.Continuous Improvement: Identify opportunities for process improvement and efficiency gains in the chip design workflow. Stay informed about industry trends and emerging technologies.
Key Responsibilities (continued)
6. RTL Design and DFT Integration : Oversee the development and optimization of Register Transfer Level (RTL) code using hardware description languages (HDLs) such as Verilog or VHDL. Integrate Design for Testability (DFT) techniques into the RTL design phase, ensuring efficient test coverage for manufacturing testability. Collaborate with DFT engineers to implement scan chains, built-in self-test (BIST), and other DFT structures in the RTL code.
7. RTL Manipulation for DFT : Lead RTL manipulation efforts to enhance DFT capabilities, ensuring observability and controllability of internal signals for testing. Implement DFT-friendly coding practices and RTL modifications to improve testability and reduce manufacturing test costs.
8 . RTL Coding Guidelines and Code Review : Enforce adherence to industry-standard RTL coding guidelines for consistency and maintainability. Conduct and participate in code reviews to ensure high-quality RTL code.
9. Digital Verification: Oversee functional verification methodologies, including SystemVerilog and Universal Verification Methodology (UVM). Ensure the creation and execution of effective testbenches for verifying the correctness of digital designs. Perform gate-level netlist verification to validate the integrity of the design at the gate level, ensuring consistency between the RTL description and the synthesized netlist. Conduct Multi-Voltage Domain verification using UPF, ensuring proper functionality and power management across different voltage domains in the system-level design.
Key Responsibilities (continued)
11. Technology Node Migration: Navigate and adapt designs to different technology nodes, ensuring compatibility and leveraging advancements.
12. Multi-Voltage Design: Manage designs with multiple voltage domains(multi voltage, power shut down), incorporating and verifying level shifters, isolation and power switch techniques.
13. Hierarchical Design and IP Integration: Oversee the optimization of hierarchical designs for scalability and ease of integration. Coordinate the integration of third-party Intellectual Property (IP) blocks.
14. Tapeout Process: Guide the team through the tapeout process, collaborating with foundries for successful chip fabrication.
Qualifications:
• Masters in VLSI design from reputed universities like IIT/NIT with background in Bachelors in Electronics and Communication, or a related field.
• 7+ years of experience in the field of semiconductor chip design.
• Proven experience in project management, with a focus on the front-end stages of semiconductor chip design.
• Strong technical background in digital design, verification, and synthesis.
• Excellent leadership and communication skills.
• Familiarity with project management tools and methodologies.
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Preferred Skills:
• Project Management Professional (PMP) certification is a plus.
• Experience with Electronic Design Automation (EDA) tools specific to front-end design.
• Knowledge of industry standards and best practices in semiconductor front-end design.
• Familiarity with Agile methodologies.
Contact
Uday
Mulya Technologies
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