Senior Design Verification Engineer - Hyderabad, India - Microsoft

    Microsoft
    Microsoft Hyderabad, India

    3 weeks ago

    Microsoft background
    Description

    Microsoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. Microsoft's Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high-performance Azure cloud servers, clients, and augmented reality.

    We are looking for a design verification engineers to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must be a highly motivated self-starter who will thrive in this cutting-edge technical environment.

    Additional Locations:

    India, Karnataka, Bangalore

    Bangalore, Karnataka

    India

    India, Uttar Pradesh, Noida

    Noida, Uttar Pradesh

    India

    Qualifications:

    • 7 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP's
    • In depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments.
    • Solid understanding of computer architecture
    • Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
    • Scripting language such as Python or Perl

    Desirable:

    • Hands on experience in Formal property verification
    • knowledge in high-speed protocols like DDR, PCIe, Ethernet
    • Processor based testbenches and emulation

    #SCHIEINDIA

    Responsibilities:

    The AISoC silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom IP and SoC designs that can perform complex and high-performance functions in an extremely efficient manner.

    • Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios.
    • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
    • Develop tests using UVM or C/C++
    • Analyse and debug test failures with designers to deliver functionally correct design.
    • Identify and write functional coverage for stimulus and corner cases.
    • Close coverage to plug verification holes and meet tape out requirements.

    Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.

    Industry leading healthcare

    Educational resources

    Discounts on products and services

    Savings and investments

    Maternity and paternity leave

    Generous time away

    Giving programs

    Opportunities to network and connect