- Implementing clock structures in multi-clock designs.
- Working on high-density designs exceeding 2.5M instances.
- Achieving challenging power, performance (timing), and area objectives.
- Experience in achieving low-power design objectives would be a valuable addition.
- Preference for experience with 3nm/4nm designs on TSMC/Samsung processes.
- Capability to predict and resolve design issues proactively and efficiently.
- Thorough understanding of the RTL2GDSII flow, encompassing synthesis, place & route, CTS, timing closure, and layout completion.
- Accountability for one or more physical design partitions.
- Capability to handle diverse constraints: Timing [of high frequency], PV, LEC, and power consumption in deep submicron designs.
- Proficient in automation with PERL, TCL, and tool-specific scripting on leading Place & Route tools (Cadence/Synopsys flow).
- Ability to manage multiple tasks and adapt to a global work environment (PPA trials to ensure a top-notch design environment).
- PNR: Proficiency in ICC2/FC (Fusion Compiler) & Innovus.
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Senior Physical Design Engineer - Bengaluru, India - Synapse Design Inc.
Description
Minimum Qualifications:
Bachelor's or Master's degree in Electronics Engineering or equivalent.
Experience: 8 to 15 years of relevant experience.
Job Role:
We are in search of a Graphics Processing Unit (GPU IP) Physical Design expert with specialization in one or more of the following:
Signoff:
Primetime for Timing, Calibre for DRC/LVS.
If this opportunity aligns with your expertise, please share your resume for consideration.
