Senior ASIC/Layout Design Engineer (BB-584BD)
Found in: Neuvoo IN
Job Description and Requirements
Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure.
Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world’s most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.
Founded in 1986, $2.7B+ Synopsys employs 12,000+ headquartered in Mountain View, California, located globally in over 25 countries with 113+ offices throughout North America, Europe, Japan, Asia, and India.
Synopsys is committed to fostering an environment that treats people with respect, honesty and professionalism. We’re also committed to partnering with the communities in which we work. Every year, Synopsys reaches out to local communities with resources and employee leadership to support education, science programs and a variety of other activities.
Come and be part of a collaborative team environment that innovates and develops the latest IP solutions that enable the way the world designs. Join US!
Senior II Analog/Mixed-Signal Layout EngineerAs a Senior II A&MS Layout Engineer you will collaborate in the development of advanced analog integrated circuit designs using best-in-class Synopsys suite of tools. You will be working with local and global teams in developing layout for complex mixed-signal designs in the latest technology nodes. In your role you will be responsible for taking on top-level block ownership with technical expertise and skills. There will also be opportunities to act as analog layout technical lead where you will be coordinating with other team members in designing and reviewing layout designs.
As a member of our Solutions IP Design Group you will be developing IP in various technology nodes and foundries for different customers in a fast paced and exciting design environment.
- In depth familiarity with layout of analog and mixed signal CMOS circuits
- Experience in development of SERDES subcircuit layout (ie. RX, TX, PLL, etc…)
- Experience in the following layout design techniques:
- Optimization for signal integrity (ie. clock/data routes, differential routing, shielding)
- Implementation of ESD design constraints, latch-up risk mitigation
- Familiarity with custom digital layout (logic cell layout and associated logic path routing)
- Layout design for reliability (ie. EM, IR, etc…)
- Design to optimize for parasitic layout effects (ie. matching, reliability, proximity effects, etc…)
- Familiarity in design for porting techniques
- Full custom analog layout design tool: Custom Compiler (or equivalent)
- Verification tools: ICV, Calibre, Star-RCXT, PERC
- Experience in working with Jira/Atlassian (or other such) tools
- Strong working knowledge of MS Office Suite of applications
- Exposure to scripting (ie. TCL, PERL, etc…)
- Typically requires an MSEE or BSEE with a minimum of 8+ years of related experience, experience in a technical lead role is a benefit.
- Can work independently to debug and resolve a wide range of issues in creative ways.
- Understands fabrication flows and physical background behind layout design flows and techniques.
- Is able to perform in a project leadership role and contribute to complex design tasks in collaboration with analog circuit design and ASIC digital design teams.
- Can prepare and present technical layout design material for internal and external audiences.
- Represents team in cross-organizational initiatives and discussions.
- Acts in a mentorship role for junior peers to support training, review and enablement for growth and development.
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