Principal Design Engineer (BB-6FD61)
Found in: Talent IN
Description:Functional Verification Engineer for DDR Memory Controller and Phy IP development team. Position is based in Noida. The role would include functional verification of the DDR Memory Controller and Phy IP solution of Cadence. The work involved will be working with the existing functional verification environment, addition of new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage. The engineer would be responsible to ensure that the design is in line with the technical and quality requirements set for the team particularly with respect to functional and code coverage. Position Requirements BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer, with a large portion of the recent work experience on verification environment development. Strong background on functional verification fundamentals, environment planning, test plan generation, environment development are a must. System Verilog experience and experience with UVM based functional verification environment development is required. Prior RTL Design experience using Verilog is a must so that the verification engineer is self-sufficient for most aspects of debugging. Latest DDR Protocol experience is highly desirable. Prior experience in functional verification and debugging of complex protocols is a must. AXI3/4 experience is a desirable. Prior experience in IP development teams would be an added advantage. Were doing work that matters. Help us solve what others cant.
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