Qualcomm

Serdes Phy Digital Design Engineer, Lead/Staff (BB-FEFF6)

Found in: Talent IN

Description:
Job Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. GENERAL SUMMARYJob Function High-speed serial link (SerDes PHY) design team is looking for talented PHY Digital designers (DD) for its Bangalore location. The team is involved in analog circuit design, layout, PD and post silicon validation of standard links (USB, UFS, PCIe, DSI, CSI) and proprietary custom links and is looking to expand for FE DD design and architecture definitions. Our team closely interfaces with various teams across the globe (San Diego/Singapore/Ireland). Responsibilities Digital FE ImplementationSynthesis & PPA optimization analysis. Must be able to create synthesis constraints based on design requirements. UPF Writing, Power Aware Equivalence checks and Low Power checks on Netlist. Use Conformal ECO flow to perform ECOs. Hands-on experience in writing scripts for quicker design turnarounds (PERL/Python). DFT Insertion and ATPG Analysis for best SAF, TDF coverage. Provide support to SoC Integration, constraints development and timing closure. Contribute and drive quality/cycle time improvement methodologies as a part of the development process. Digital FE DesignMicro-architecture development and implementation Quality checks of the implemented RTL for clock-domain crossing (CDC, Spyglass, 0in), Linting (Spyglass) and DFT rules with clear documentation of exceptions and waivers. Low Power Analysis on RTL using LEC. Provide quality documentation of IP implementation and other deliverables post design reviews. Work closely with IP and SoC verification teams to achieve high quality IP delivery. Work closely with Analog designers and propose feature enhancements. Skills & Experience Master/Bachelor in Electronics, Working experience (2-6 years) Expertise in micro-architecture development and RTL coding. Good understanding and hands-on experience in mixed-signal IP design with bus protocols like USB3.0, USB2.0, SPI, I2C, UART, XRAM, APB, etc. Experience with high-speed SerDes Design will be an added advantage. Experience with post-Si bring-up and debug is a plus. Excellent verbal and written communication skills. Able to work with teams across the globe and possess good communication and presentation skills. Job Function High-speed serial link (SerDes PHY) design team is looking for talented PHY Digital designers (DD) for its Bangalore location. The team is involved in analog circuit design, layout, PD and post silicon validation of standard links (USB, UFS, PCIe, DSI, CSI) and proprietary custom links and is looking to expand for FE DD design and architecture definitions. Our team closely interfaces with various teams across the globe (San Diego/Singapore/Ireland). Responsibilities Digital FE Implementation Synthesis & PPA optimization analysis. Must be able to create synthesis constraints based on design requirements. UPF Writing, Power Aware Equivalence checks and Low Power checks on Netlist. Use Conformal ECO flow to perform ECOs. Hands-on experience in writing scripts for quicker design turnarounds (PERL/Python). DFT Insertion and ATPG Analysis for best SAF, TDF coverage. Provide support to SoC Integration, constraints development and timing closure. Contribute and drive quality/cycle time improvement methodologies as a part of the development process. Digital FE Design Micro-architecture development and implementation Quality checks of the implemented RTL for clock-domain crossing (CDC, Spyglass, 0in), Linting (Spyglass) and DFT rules with clear documentation of exceptions and waivers. Low Power Analysis on RTL using LEC. Provide quality documentation of IP implementation and other deliverables post design reviews. Work closely with IP and SoC verification teams to achieve high quality IP delivery. Work closely with Analog designers and propose feature enhancements. Skills & Experience Master/Bachelor in Electronics, Working experience (2-6 years) Expertise in micro-architecture development and RTL coding. Good understanding and hands-on experience in mixed-signal IP design with bus protocols like USB3.0, USB2.0, SPI, I2C, UART, XRAM, APB, etc. Experience with high-speed SerDes Design will be an added advantage. Experience with post-Si bring-up and debug is a plus. Excellent verbal and written communication skills. Able to work with teams across the globe and possess good communication and presentation skills. Minimum Qualifications Education:Bachelors - Computer Science, Bachelors - Engineering, Bachelors - Information Systems Work Experiences:4+ years Hardware Engineering experience or related work experience. Certifications: Skills: Preferred Qualifications Education: Work Experiences:2+ years experience with circuit design (e.g., digital, analog, RF). ,2+ years experience utilizing schematic capture and circuit simulation software. ,2+ years experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. ,1+ years in a technical leadership role with or without direct reports. ,6+ years Hardware Engineering experience or related work experience. Certifications: Skills:Computer Science, DSP Architectures, Electrical Engineering, Optical Systems, Packaging Systems

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