Description:

Exp 2-5 Yrs Verification UVM, SV expertise Should be experienced in IP level functionality verification, testbench component design, concepts of constrained-random verification, SV assertions and coverage closure Should have excellent verbal/written communication skills Exp 5-8Yrs Experience in Testbench Developement using System Verilog and UVM methodology. Good in testcases/sequences coding. Good at code coverage and functional coverage Good Working knowledge on Protocols (AXI, PCIE and AHB). Good debugging skills. Strong in System Verilog, Verilog and UVM methodology. Basic Knowledge in specman e language and scripting. Exp 8-12Yrs Experience in Testbench Developement using System Verilog and UVM methodology. Good knowledge on ethernet MAC, PHY and WLAN protocols 802.11X. Knowledge on Gate level simulations(GLS). Working knowledge on SoC verification. Good in testcases/sequences coding. Good at code coverage and functional coverage. Good Working knowledge on Protocols (AXI and AHB). Strong debugging skills. Strong in System Verilog, RAL,UVM methodology.