Signal Integrity Engineer (BB-B0196)
Found in: Talent IN
Description:Job DescriptionAre you passionate about computer graphics and disrupting the industry with your innovations? Working with leading engineers on Intel's latest GPU/CPU architecture? Do you love collaborating with diverse teams, customers, and design partners to help achieve Best–In-Class visual experiences that enable users to immerse themselves in a new visual future? If you answered yes to any of these questions, then our IAGS organization has opportunities for you. In IAGS we deliver Intel's integrated and discrete GPUs, which include 3D graphics, multimedia/video, 4K+ display, and parallel computing technologies. Our Platform Architecture and Engineering (PAE) team drives the platform solutions for Intel's entry into market segments served by high performance discrete graphics processors and hardware.The Discrete Graphics Platform Architecture and Engineering (PAE) team is hiring multiple roles with diverse expertise in our Bangalore office. As a member of this team we are looking for Power Integrity Lead & Power Integrity Engineers.In this position you will be responsible for providing package and platform power integrity solution for Intel graphics products. You will also be required to architect package and board power integrity solution such as voltage rail merging and isolation scheme, stack up and decoupling cap type and to provide design constraints for and guide implementation of component packages and boards to meet design targets. You will also be focusing on design processes, techniques including electrical model extraction, development and simulation from Direct Current (DC) to high frequency component on full system power delivery network. End goal is to deliver optimized platform electrical solution within the boundary condition followed by design validation and correlation for continuous methodology enhancement.Your responsibilities will include but not be limited to:Performs comprehensive simulations and validations to generate Intel design guidelines to guide system level power integrity design including, but not limit to, silicon, package, socket, boards and voltage regulators.Performs AC and transient simulation to provide impedance profile of the whole power delivery path, from the VR to the motherboard, the package and the die.Provides guidance to the design team on capacitor numbers & values and power plane shape & width.Correlating simulations with system measurements.Deliver optimized PI solution meeting the product performanceProvides DC and resistance simulation to provide Rpath from the VR to the package pins, voltage drop, current density and power loss analysis.Performs transfer impedance simulations to provide plane split and isolation guidance between interfaces on board package area.As a lead, you will be expected to mentor & guide other team members, develop a strong network across organizations and geographies, propose and lead strategic contributions, and role model Intel values.QualificationsCandidate must possess a bachelor’s degree or higher in Electrical or Electronic Engineering or Ph.D. in a power integrity engineering related area.Minimum 6 years of experience in Silicon, package & board level power integrity design.Solid understanding of theory on power integrity as well as having applied it to actual designs in the industry or in the academy.Power Integrity simulation software use such as Sigrity PowerSI, PowerDC, HSpice and Matlab.Package/board routing CAD tools such as Cadence Allegro and Mentor Graphics.Hands-on experience with lab equipment for correlationWorking knowledge of board-level system architecture, basic silicon design & packageKnowledge in PCB layout process and methodology.Ability to clearly communicate routing rules to layout designers and work with them for successful project release.Ability to communicate effectively across multiple disciplines, such as silicon design, package design, board design, PCB layout, and mechanical design.Great team player, willing to learn and flexible.Solid verbal and written communication skills are required.Ability to work effectively in a dynamic team environment.
calendar_today3 days ago