IP/SOC Design Methodology and Flows Engineer (BB-430F6)

Found in: Talent IN

Job DescriptionThe IAGS GTCHE (Graphics and Throughput Computing Hardware Engineering) organization is responsible for the development of Graphics IPs & discrete GPU SOCs.The FE-TFM team within GTCHE is responsible for providing methodologies for Best-In-Class RTL development, IP delivery, SOC integration and execution, and verification. The team develops and deploys these methodologies across all graphics IPs & SOCs. We are looking for a talented Front End Design Methodology Engineer to join our team. In this position, you will work on RTL design, integration & quality checks related flows across clusters, IP, Subsystems, SOCs. You will rapidly take features from concept to production and provide customer support, debug failures, and provide out of the box solutions.Responsibilities:Understand and enhance the frontend design flows and methodologies across IPs and SOCs to identify key areas of improvementProvide user friendly solutions, to increase productivity of teamIdentify, define & publish the best practices for the various aspects related to RTL development, IP delivery, SOC integration, quality checks and back-end handoffQualifications5 years experience in IP, SOC design and/or integration or RTL design experience.3 Years of experience with system Verilog and familiarity with a range of internal and 3rd-party logic design toolsExperience in FE development flows and tools (Verilog design language, VCS, SpyGlass etc.)

calendar_today5 days ago


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location_on Hyderabad, India

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