Description:

Job Description

In this position you will be involving in the design and development of next generation IP Cores for Intels FPGAs ASICs and SASICs Your responsibilities will include some of the following but not limited to o Register Transfer Level RTL development and functional validation Use Intel FPGA design tools extensively to simulate logic behavior and circuit performance for next generation IP solutions for Intels FPGAs ASICs and SASICs Verify the circuit behavior against the original simulation model and in silicono Responsible for Integration and maintenance of IPs Synthesis functional verification timing closure and debug of IPs in hardware

Qualifications
You should be a student PhD Masters ME MTech MS currently pursuing studies in relevant field with good understanding of semiconductors HDL RTL design and verification FPGA design Additional qualifications includeo Familiarity with logic circuit designo Knowledge of Verilog System Verilog FPGA design FPGA design softwareo Exposure to high speed serial protocols PCIeEthernet will be preferredo Capable of building block and system level testbench from scratch using System Verilog experienced in UVM constrained random coverage driven concepts assertion based verification and functional coverage techniqueso Knowledge and experience in UVMVMMOVMo Experience in Design and verification tools simulation tools and debug toolso Endtoend System level experience including design software firmware and hardwareo Good programming skills C C perl python tcl etco Well versed in FPGA design and FPGA design tools