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- Review and ensure current team members completed verification tasks are done with quality ( review sim , UVMscoreboard / checker codes review , tests review, function coverage points , SVA Verification domain knowledge excellence – UVM/VCS/Verdi/System Verilog/SVA/Coverage
- Drive and enable current TechM verification members daily verification activity, lead team to finish in-progress tasks on schedule and unblock them whenever they need technical guidance to make progress ( regression failing debug Leadership and Debug Guidance
- Lead team to work on co-simulation environment UVM + C ( RTL + Firmware) to run mix-and-match block gate level/RTL simulation at full chip level. – Hardware/firmware co-simulation, gate level simulation
- Collect and prepare Daily team progress report from Client– Management
Technical Lead - Bengaluru, India - Tech Mahindra
Description
Exp 12 +