Senior / Lead DFT Engineer - Kottayam - Silicon Patterns

Description

Senior DFT Engineer

Location: Bengaluru, India

Experience: 3–12 Years

Role Type: Full-time | Silicon Engineering

About the Role

We are seeking a Lead Design-for-Test (DFT) Engineer to drive RTL-centric DFT architecture and execution for complex SoCs and subsystems used in high-performance compute, AI acceleration, and advanced connectivity platforms.

You will own the complete DFT lifecycle — from RTL insertion strategy through pattern generation, simulation, and silicon-quality coverage closure — while partnering with design, physical implementation, and post-silicon teams to ensure first-pass success.

This role is ideal for engineers who combine deep hands-on DFT implementation with system-level thinking and execution excellence.

What You'll Do

• Lead RTL-level DFT architecture and implementation across full SoC and block/partition hierarchies
• Own DFT flows using Mentor Tessent across:
• Scan insertion
• MBIST
• OCC (on-chip clocking)
• EDT compression using ARM DFT flow
• Drive LEC (Logical Equivalence Check) at:
• RTL pre-DFT vs post-DFT
• RTL vs gate-level netlists
• Execute pattern generation, retargeting, and simulation at block and SoC level
• Perform zero-delay and timing-aware simulations using SDF back-annotation
• Drive coverage closure across stuck-at, transition, and memory faults
• Develop scan synthesis flows and timing constraints aligned with physical design requirements
• Partner with PD teams to ensure timing-clean DFT insertion
• Debug test failures through simulation and silicon correlation
• Mentor engineers and review DFT architecture across projects

Interested folks can share CV at ishitaanand@silivconpatterns.com

NP- within 60 days