DFT STA Lead - Bengaluru, Karnataka

hashtag#StaticTimingAnalysis (STA) Lead | 10+ years · ...

Developing and maintaining world-class hardware design flow in fast-paced production environment on the very edge of modern technology. · ...

Technical Skills: · Well versed with the timing closure (STA), timing closure methodologies. · Pre/Post-layout constraint development to timing closure. · Handshake with the design team and develop functional/DFT constraints. · IP level constraint integration. · Multi-voltage/Swi ...

Lead STA Engineer · Experience: 10+ Years · Location: Bangalore · Job Summary: · We are looking for a highly skilled STA Engineer with 10+ years of experience in timing analysis and closure for complex IP and SoC designs. The candidate will be responsible for driving block-level ...

The job requires experience of STA tool Tempus/PrimeTime /Tweaker/ DMSA(PTECO) and knowledge of timing corners/modes, process variations and signal integrity related issues. · ...

STA Lead Engineer required for Semiconductors / VLSI /STA Engineers industry in Bangalore. Experience of STA tool Tempus/PrimeTime /Tweaker/ DMSA(PTECO) needed. · ...

The Role The focus of this role will involve driving the physical design flow from timing through final sign-off collaborating closely with cross-functional teams to meet stringent power performance and area (PPA) targets on SerDes PHY IPs. · ...

We are hiring a STA Engineer for our Bangalore location. · ...

Work with design and architecture teams to define timing constraints for designs. · ...

+At MediaTek, candidate will be responsible for end-to-end DFT STA including SDC creation in all modes. · ...

DFT STA Lead engineer responsible for end-to-end DFT STA including SDC creation in all modes, SDC sanity checks, CCD, DFT CTS sanity clean up and DFT all mode timing closure both top and block. · ...

· Overview · Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead Static Timing Analysis Engineer to join our STA team in Bangalore. In this role, you will be working with some of the brightest inventors and engineer ...

Achieve timing closure for next-generation CPU/APU designs operating at industry-leading frequencies. · 10+ years of experience in Static Timing Analysis · 5+ years working on CPU, GPU, or high-frequency ASIC designs · ...

Overview · Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead Static Timing Analysis Engineer to join our STA team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers i ...

We seek an experienced Static Timing Analysis (STA) Lead to join our high-performance Cores team. This role will ensure timing closure and optimization of next-generation CPU/APU designs operating at industry-leading frequencies. · ...

STA and Timing closure of Infineon SoCs targeted for IoT and MCU markets. · In your new role you will lead STA and Timing Closure of complex low power SoCs targeted for IOT and MCU markets. · ...

We are looking for a highly experienced STA/Timing CAD Methodology Lead to own architect and scale the next generation of static timing analysis methodologies for cutting-edge high-performance SoC designs. · Define develop and deploy industry-leading STA and ECO methodologies acr ...

Company · Qualcomm India Private Limited · Job Area · Engineering Group, Engineering Group > Hardware Engineering · General Summary · We are looking for a highly experienced · STA/Timing CAD Methodology Lead · to own, architect, and scale the next generation of static timing anal ...

In your new role you will lead STA and Timing Closure of complex SoCs targeted for IOT and MCU markets. · ...

As the SoC Timing Lead/Principal Engineer at Semifive India Design Centre in Bengaluru, you will play a critical technical leadership role in delivering first-time-right silicon for global customers. · The role offers broad ownership and real impact, where timing and synthesis le ...