RTL Engineer - Bengaluru, India - Hiringlabs Business Solutions

Description

3 to 5 years of work experiencein ASIC/SoC Design.
Experience in Logic design / RTL coding is amust. Experience isSoC design and integration for complex SoCs is amust. Experience inVerilog/SystemVerilog is amust. Experience inMulti Clock designs Asynchronous interface is amust. Experience inusing the tools in ASIC development such as Lint andCDC. Experience inSynthesis / Understanding of timing concepts is aplus. Experience inECO fixes and formalverification.
Should have knowledge of AMBA protocols AXI AHB APB SoCclocking/resetarchitecture.
Excellent oral and written communicationsskills. Proactivecreative curious motivated to learn and contribute with goodcollaboration skills
rtlcoding,cdc,asic developmenttools,rtl,lint,asic,ahb,synthesis,written communication,multi clockdesigns,logic design,system-verilog,asynchronous interface,ecofixes,apb,oral communication,formal verification,ambaprotocols,axi,soc clocking/reset architecture,soc design,systemverilog,verilog,collaboration