RV PDK Engineer - Bengaluru

The role focuses on automation of PDK verification (LVS, DRC, PEX, Spice), web hosting of test results, and AI/ML analysis to enhance efficiency. · Develop and maintain Python/Perl/Tcl/Shell scripts for endtoend PDK testing. · Set up and manage CIcompatible web servers (Jenkins, ...

In your first year with TI, you will participate in the Career Accelerator Program (CAP), which provides professional and technical training and resources to accelerate your ramp into TI and set you up for long-term career success. · ...

We are seeking an experienced RV PDK Engineer to develop, maintain, · and support PDK collateral for advanced semiconductor process nodes. · Develop, validate and maintain · PDK collateral across multiple technology nodes · Build and support DRC,LVS,,ERC,and PERC rule decks · ...

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify and test electronic systems that launch cutting-edge products. · ...

We’re looking for an EDA Engineer who lives and breathes SKILL, OpenAccess, and PDK/CDK enablement. · We're looking for an EDA Engineer who lives and breathes SKILL, OpenAccess, and PDK/CDK enablement.Cadence Virtuoso (Analog / Mixed-Signal flows) · Skill scripting & advanced CDF ...

We're looking for an EDA Engineer who lives and breathes SKILL, OpenAccess, · and PDK/CDK enablement. ...

We're looking for a Senior EDA Engineer to help build and scale automation for an AI-powered analog design platform. · Build and optimize analog/mixed-signal design flows in Cadence Virtuoso · Develop SKILL scripts for schematic, layout, and verification automation · ...

We are looking for a Senior EDA Engineer with strong hands-on expertise in Cadence Virtuoso, SKILL scripting, · and Open Access (OA) to help build scalable,intelligent design flows for next-generation analog IC design. · This role will work closely with AI, EDA,and platform engin ...

We are seeking a highly skilled EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. · ...

+We are seeking a highly skilled EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration and schematic/layout tool automation. · +Develop, maintain and optimize analog/mixed ...

Senior EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. · • Develop, maintain, and optimize analog/mixed-signal IC design flows ...

Job Description: · The Analog Layout Engineer is responsible for designing and optimizing analog layouts for advanced semiconductor process technologies. · Designs and optimizes analog layouts using Cadence Virtuoso, Mentor Graphics, Synopsys IC Compiler or equivalent tools · Has ...

We are looking for a Senior EDA Engineer with solid experience in Cadence Virtuoso environments and a deep understanding of OpenAccess databases, SKILL scripting, foundry PDK/CDK integration, and schematic/layout tool automation. · Develop, maintain, and optimize analog/mixed-sig ...

The Foundation IPs and PDKs engineer is responsible for the systematic organization, maintenance, and distribution of all FIP and PDK assets such as Standard cells libraries, Memory compilers, EDA tools tecfiles and runsets. · This role involves the efficient tracking, retrieval, ...

Analog Circuit design Engineer responsible for performing analog circuit design for high-speed I/O blocks and executing design simulations. · ...

Design analog circuits for high-speed I/O blocks. Execute design simulations and work on layout back-annotation. · Perform analog circuit design for high-speed I/O blocks (buffers, receivers, transmitters) · Work on design changes, not just verification, ensuring compliance with ...

+ Lead a team of physical design engineers to deliver high-quality results on time. · + Develop and maintain expertise in latest PDKs from Synopsys Custom Compiler. · 10-20 years of experience in Physical Design, Floor Planning, ICC, Timing Analysis, and Physical Verification usi ...

+Job summary · Tata Electronics is building India's first AI-enabled state-of-the-art Semiconductor Foundry. · +ResponsibilitiesHands on experience with RTL to GDSII, sign-off & timing closure. · ...

+Job summary · Tata Electronics is building India's first AI-enabled state-of-the-art Semiconductor Foundry. The facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic.Qualifications · ...

The Foundation IPs and PDKs engineer is responsible for the systematic organization, maintenance, · and distribution of all FIP and PDK assets such as Standard cells libraries, · Memory compilers, EDA tools tecfiles and runsets.Maintain a comprehensive · and up-to-date inventory ...