Senior Vice President. - Bengaluru, India - Mulya Technologies

Description

SVP Physical Design

SVP- Physical Design PracticeLocation: BangaloreReporting : to CEO

About the jobLarge IT Services and Solution Organization is hiring a practice head (SVP)for physical design stream for the semiconductor division.

As a practice head you will be responsible for defining methodology, work on complex full chip implementations

The candidate should be well versed with lower nodes preferably upto 3nm.

The individual should be seasoned enough to have setup full chip PD flow (hands on) multiple times and should be able to comprehend nuances with respect to front end design, DFT and system design to work seamlessly with these teams to ensure the functional, performance and power goals of the chip are met.

The candidate should be knowledgeable of complex power architecture, place and route, timing closure,

STAPhysical VerificationDFTPDNCADHe/She will also be responsible for competency of the entire team and will work towards building capabilities of the team.

Therefore, the individual should be a good mentor and a teacher. He/She should drive hiring initiatives and also focus on building large and capable teams meeting the customer's challenges.
QualificationsElectrical engineering or electronics engineering B Tech, M.

Tech or PhD degree from Tier1 College20-30 years of relevant experience in the conception through to production of high speed ASICsShould have done hands on work in full chip PD flow including, power planning, Place and Route, Timing closure,Requires practical knowledge of all phases of VLSI development as well as a track record of working with different stakeholders like architecture, software, design, DFT and foundry services to ensure effective synchronization with other domains are understood and addressed.

Core CompetenciesPHYSICAL DESIGN (IP/SOC)STADFTPhysical VericationPDNCAD

CHIP SIGN-OFF

Leadership Skills CUSTOMER ENGAGEMENTPROGRAM MANAGEMENT (PMP) AGILE/SCRUMPEOPLE LEADERSHIP

from Top15 Semicon Organizations in the worldExperience in SOC/IP projects in process nodes 14nm, 10nm, 7nm, 5nm and 3nm (RTL to Tape-out) across multiple foundry TSMC / SamsungParticipated in various SOC and IP designs catering to client processor /server microprocessor /DSP /mobile and IOTG segment in many designsInvolved across breadth of semiconductor domains that includes EDA tool development, flow development and chip design and tape-outs.

Architected a new digital design flow that provided benefits such as supporting Synopsys Fusion Compiler and Cadence Innovus implementation solutions with scalable architecture compatible with different types of designs in client, server, mobile or IOT chips and supporting internal process technology & external TSMC processFormulated various convergence milestone definitions, check points, convergence status reporting restructuring and automation in flows to streamline the convergence process while guiding a reliable & performing team to handle complex SOCHeaded TSMC 3nm platform enablement for physical design for server, client and IOT class of designs; successfully enabled test chip tape-ins and many programs start on TSMC 3nm

Professional ExperienceKey Result Areas:
Proven technical leadership during program execution of complex requirements in terms of schedule, performance power and cost through the complete design cycle from program conception, scoping, execution through to commercial sample releaseCollaborating with vendors to assess their technology and to guide their product roadmap based on requirements Providing pro-active leadership in area involving assessing the requirements from stakeholders, building innovative solutions that continually advance tools & processes, and coordinating deploymentDeveloping competency among the team members; managing appraisal process across the levels, conducting interviews to recruit the right talent & resources, and developing employee competencyHighlights:Demonstrated reputation for building & leading global teams while leveraging out of the box thinking for delivering higher gains, optimizing capabilities, and meeting assigned responsibilities:o Facilitated many designs for digital backend tools/flows & methodology;new architecture, TSMC 7nm ,5nm and 3nm and server with > 500mm2 die sizeo Introduced integration initiative of Tempus, Quantus, and Voltus from cadenceinitiated Timing Eco Tool tweaker in addition to primetime eco solution and enabled Mentor Calibre for all TSMCnodes in design in addition to existing solution based on ICV

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