Senior Design for Test - Hyderabad, Kondapur, India
2 days ago
Job summary
+Senior Engineer responsible for Scan insertion and validation, BIST, MBIST insertion and validation ATPG IP Tests and Pattern validation w/wo Timing DFT mode timing Analysis sign off.
+Responsibilities
+- Be responsible for a comprehensive DFT plan
- Incumbent to work with DFT cross functional teams
- Arcitect implement solutions for Scan built-in self-test (Memory Logic BIST) circuitry to test devices in the field
Job description
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