Verification Expert - Kurnool - beBee Careers

Job title: Senior Design Verification Lead

Description

Senior Design Verification Lead

About the Role:

We are seeking an experienced Senior Design Verification Lead to lead our SoC Design Verification efforts. The successful candidate will be responsible for developing and implementing comprehensive verification strategies, ensuring successful execution of verification plans, and collaborating closely with cross-functional teams.

Main Responsibilities:

• Develop and implement comprehensive verification strategies, including test plans, testbenches, and coverage analysis, for complex projects.
• Lead gate-level simulations and power-aware verification using tools like Xprop and UPF.
• Analyze and implement System Verilog assertions and functional coverage to ensure thorough verification of design functionality.
• Provide mentorship and technical guidance to junior verification engineers.
• Ensure that all verification signoff criteria are met, with clear and comprehensive documentation.

Requirements:

• 5+ years of hands-on experience in SoC Design Verification.
• Expertise in verification of high-speed SoCs and various protocols, including I2C/I3C, SPI, UART, GPIO, QSPI, PCIe, Ethernet, CXL, MIPI, DDR, and HBM.
• Proficiency in System Verilog for verification, including assertions and coverage.
• Experience with gate-level simulations and power-aware verification using Xprop and UPF.
• Strong hands-on experience with VCS and Xsim from Synopsys and Cadence.
• Mentorship experience, providing guidance to junior engineers and managing verification teams.