ASIC Design Verification - All India

You will be responsible for utilizing your expertise in Electronics, Electrical, Computer Engineering or Computer Science Engineering to contribute to the success of the team. · BE/BTech/MTech/MS/PhD in Electronics, Electrical, Computer Engineering or Computer Science Engineering ...

Job summary · ...

You will be responsible for Design Verification using UVM, SV, and Ethernet for a work location in Hyderabad/Bangalore. · Perform Design Verification tasks using UVM methodology. · Write and execute test cases in SystemVerilog. · Verify Ethernet designs and ensure functionality. ...

You will be responsible for leading the design verification activities for chip solutions. · ...

As a Verification Engineer you will be responsible for verifying complex designs using advanced methodologies like UVM and Formal DV. · ...

You will be responsible for developing software solutions and investigating problem areas throughout the software development life cycle. · ...

As an experienced candidate with 2-3 years of experience. · ...

Developing Assertion Based Verification packages and tools, creating Assertion test plans for various protocols, and conducting full chip verification using Verilog, C, and Object Oriented Programming. · ...

As a Senior Design Verification Engineer at Silicon Patterns you will be responsible for leading verification activities for complex IPs/SoCs with expertise in Ethernet protocols. · ...

A Senior Design Verification Engineer will work on a large ASIC project conducting gate level verification setting up testbenches for testing debugging x-propagations. · ...

Developing SV / UVM test benches and coding test cases Analyzing and closing code and functional coverage Collaborating with the team to achieve verification closure Utilizing experience with Python or any other scripting language Having working knowledge of bus protocols such as ...

· As a Low-power SoC DV Engineer, your role will primarily involve full-chip/sub-system verification, power intent validation, and advanced debugging. Your responsibilities will include: - Experience in full-chip SoC/sub-system verification with UPF, with a majority of project e ...

· Role Overview: You will be responsible for SOC verification as a Lead Design Verification Engineer. Key Responsibilities: - Lead the design verification activities for SOC. - Develop verification test plans and strategies. - Design and implement test benches. - Run simulations ...

You have an opportunity to join as a BUS Interconnect Expertise with the following responsibilities: · Design Verification of BUS Interconnect blocks of Modem Sub-system and SOC level · Required experience of 3.5 years to 4+ years · ...

· You will work on verifying next-generation CPU features with a focus on functional correctness, coverage, and debug. This role offers strong exposure to microarchitecture-level verification and advanced simulation environments. - Experience in ASIC CPU verification - Solid han ...

Designing and developing innovative engineering solutions collaborating with cross-functional teams to ensure project success providing technical support and guidance to clients. · ...

As an Engineer at eInfochips in Bangalore, India you will be responsible for designing and developing engineering solutions collaborating with cross-functional teams to ensure project success implementing best practices and innovative approaches. · ...

As a Design Verification Engineer you will be responsible for playing a key role in the functional verification of designs. · Develop block-level and system-level verification plans write test sequences execute tests and collect and close coverage. · , · ...

As a Design Verification Engineer for Ethernet, Wi-Fi, and Bluetooth IPs in Pune, your responsibilities will include: developing verification plans for Ethernet, Wi-Fi, and Bluetooth IPs building and maintaining SystemVerilog/UVM-based verification environments verifying protocol ...

We are seeking a CPU IP Design Verification Engineer to drive CPU core verification from specification to sign-off. This role requires strong experience in SystemVerilog and UVM, as well as debugging skills using VCS/Questa/Xcelium. · Demonstrating strong handson experience in Sy ...