Immediate Requirement for Engineers - Bengaluru, India - LeadSoc Technologies Pvt Ltd
Description
PD:
Experience in Block/SOC level PD Implementation flow.
Netlist to GDSII / PD / Implementation flow / PnR / APR
Low power design experience
Floorplanning, Power planning, Placement, CTS, Routing, Extraction, DFM
Congestion and timing analysis, Coming with better QoR
Sign-off flow :: STA, DRC/LVS/Antenna/ERC, Power analysis, IR/EM analysis, LEC, ECO (Timing and Functional)
Have in-depth knowledge of entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing and Sign Off ( STA, PV, IR/EM)
Experience in ECO implementation
Hands on experience in PnR tools Synopsys ICC II/ Cadence Innovus etc
Scripting skills :: Perl, TCL
• EDA Tools
Should possess good Leadership Skills
Must have good communication & problem-solving skills.
Should be with Go-getter attitude
STA:
Very good understanding of timing concepts
Should have understanding of SDC and constraints syntax
Work with the design and implementation teams to develop and qualify timing constraints
Experience in Timing Analysis both at block level and SoC level
Experience with Industry Timing signoff tools like Primetime / Tempus is a must
Experience in DMSA or Tweaker
Should have understanding of different Timing modes and Corners
Experience in MMMC
Work closely with the physical design engineers to resolve implementation related timing issues
Should be able to plan and track self execution and report result on regular basis systematically
Should be able to solve timing challenges in Block/SOC by manually closing difficult paths
Should have a clear understanding of Crosstalk delay/noise, Timing derates, AOCV/POCV concepts and its impact of design closure
Should have worked on Timing ECO generation in multi-voltage designs
Experience Timing & Noise Signoff Closure at block level or Full chip-level on advanced process nodes
Hands on scripting skills on TCL / Perl
Synthesis:
Good Experience in RTL Codes.
Should have understanding of SDC and constraints syntax.
Experience in Synthesis in both Block/SOC Level.
Good Experience in Logical/Physical/Low power Synthesis
Good Knowledge on Optimization Techniques to achieve the best Performance/Power/Area of the designs.
Experience with tools and methodologies for Synthesis - hierarchical synthesis, DFT handling, retiming, clock gating, logic restructuring, optimization.
Expertise in Synopsys Design Compiler Synthesis – DCT/DCG and/or Cadence RC/Genus.
Working knowledge of multi power domain designs.
Good Knowledge on CPF.
Knowledge on Scan Insertion.
Good in Timing Concepts.
Experience in STA/LEC/CLP.
Knowledge on PTPX.
Knowledge on Spyglass.
Knowledge on Functional ECO.
Experience with Perl/TCL.