Verification Engineer - Delhi, India - Anlage

Description

Key Responsibilities :
1) Develop testbenches for a non-volatile memory IP

2) Creation of agents

3) Make adaptations to existing and create new tests for new features of the NVM IP

4) Show that the relevant tests are passing

5) Define verification coverage

6) Testbench Qualification using Certitude

7) Documentation of verification results

8) Proof that relevant tests are passing

9) Proof that verification coverage (structural and functional) is reached

10) Proof that the testbenches have the required quality

11) TSMC relevant - Yes

12) Proven experience (>5 years) in Digital IP verification using System Verilog / UVM
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