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- Design architecture development and its review
- RTL design development
- Debug of simulations, including those of real signals modeled using SV for analog
- RTL, GLS, Co-simulations
- Deliver high quality RTL and other simulation models to customer
- Participate in technical reviews and contribute actively
- Participate in customer support with bring-up of IP in customer simulation environment
- Participate in review of SERDES / PHY / Controller IP specification to validate compliance to protocol of interest
- Follow and improve development process ensuring high quality output
- Hands on experience with HVL, or HDL like VHDL, System Verilog
- Knowledge of Perl/Shell scripts
- Knowledge of protocols like Ethernet, PCIe, other networking protocols
- The candidate should have good communication skills, be a team player with leadership qualities, good problem solving and interpersonal skills.
RTL Design Engineer - Bengaluru, India - Applied Intelligence Semiconductors Pvt Ltd
Description
Skill Set