Staff Design Verification Engineer: Server class ARM Sub-system Focused - Greater Bengaluru Area - Tsavorite Scalable Intelligence

    Tsavorite Scalable Intelligence
    Tsavorite Scalable Intelligence Greater Bengaluru Area

    4 days ago

    $100,000 - $120,000 (USD) per year
    Description

    Staff Design Verification Engineer: Server class ARM Sub-system Focused

    Bangalore

    Founded in 2023,by Industry veterans HQ in California,US

    Location: Greater Bengaluru Area

    Company Description

    We are looking for exceptional talent and leadership to join , the world's first company developing Agentic Silicon for powering the future of AI.

    Founded in 2023, our team consists of 90+ highly skilled engineers from leading companies such as Intel, Marvell, Nvidia, Qualcomm, Cisco, AMD, Apple etc. We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.

    Staff Design Verification Engineer: Server class ARM Sub-system Focused

    Job Description

    In this role you will be working on server class ARM CPUSS sub-system verification at block and SoC level. The task list includes, but is not limited to, testplan development, env development, checker/scoreboard development, test execution and analysis at sub-system, chiplet and multi-chiplet level

    Roles And Responsibilities

    • Partner with Architects and RTL Design team to grasp high-level system requirements and specifications.
    • Formulate comprehensive test and coverage plans to match the Architecture and micro-architecture.
    • Develop the verification environment and reusable bus functional models, stimulus, checkers, assertions, trackers, and coverage metrics.
    • Create verification plans and develop testbenches tailored to assigned IP/Sub-system or functional domain.
    • Execute verification plans, including tasks such as design bring-up, setting up the DV environment, running regressions for feature validation, and debugging test failures.
    • Support post-Si bring-up and debug activities.
    • Track and communicate progress in the DV process by using key metrics like testplan status, bug tracking and coverage reports.

    Requirements

    • Bachelor's or Master's degree in Electrical/Electronics Engineering/Science with 5 to 10 years of relevant experience
    • Strong Architecture domain knowledge in ARM subsystems (A-cores) including booting and code execution/debug.
    • Working knowledge on CMN (Coherent Mesh Network), SMMU (System Memory Management Unit), GIC (Generic Interrupt Controller), ARM Chip-to-Chip
    • Expertise in coherency concepts and CHI protocol
    • Knowledge of interaction of CPUSS with High performance NoCs and Memory systems
    • Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 5yrs+ hands-on experience in IP/sub-system and/or SoC level verification
    • Hands on experience and expertise with industry standard verification tools for simulation and debug (Questa/VCS, Visualizer)
    • Experience using random stimulus along with functional coverage and assertion-based verification methodologies a must.

    Preferred Qualifications:

    • Experience in development of UVM based verification environments from scratch.
    • Hands on experience doing verification on ARM CPUSS for server class design
    • Hands on expertise and protocol knowledge in any of: CHI/APB/AXI/CXS.
    • A strong drive for DV infrastructure automation

    Contact:

    Uday

    Mulya Technologies

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