Design for Test - Bengaluru, India - Cyient

    Cyient
    Cyient Bengaluru, India

    2 weeks ago

    Cyient background
    Engineering / Architecture
    Description

    Job Description

    Experience: years

    Skill Set Requirements:

    • Full-chip DFT working experience with multiple design Tape Outs
    • Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements.
    • Expertise in Scan Compression(EDT/OPMISR+), MBIST, BSCAN, ATPG implementation and verification.
    • Hands on Experience with industry standard DFT EDA tools & flows(Tessent, Synopsys, Cadence)
    • Good Knowledge of cross functional domains (SYN, LEC, STA, PD) with owner ship of constraints developments & LEC.
    • Excellent problem solving and debugging skills. Proactive in nature.
    • Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process
    • Leading junior teams, Mentoring/Training and Project leadership.
    • Excellent Customer interaction, Communication and Team work skills

    Skills & Experience

    ATPG (at-speed & stuck-at), Automatic Test Pattern Generation (ATPG), Design for Testability (DFT), Design Rule Checking (DRC), Formal Verification, Gate Level Simulation, Hardware Description Language (HDL), Test Pattern Generators