- Develop and execute test plans for SoC, including the creation of test benches, ensuring comprehensive coverage at module, subsystem, block, and chip levels.
- Create complex test cases covering control and data paths of multiple IPs at both chip and module/sub-system levels.
- Conduct reviews of test plans, milestone checklists, and manage Jira assignments.
- Conduct rigorous block and system level verification, emphasizing coverage-driven verification concepts, and defining covergroups and assertions.
- Monitor regression failures, collaborate with the team to resolve issues, and ensure timely progress.
- Verify designs involving multiple power domains using UPF/CPF.
- Collaborate closely with ASIC architecture, design, and verification teams to triage and resolve bugs and issues.
- Leverage Cadence tool set experience for simulation and analysis, including coverage collection.
- Apply competencies in System Verilog and UVM verification flows to optimize the verification process.
- Deliver verified SoC chip-level ASIC RTL, Gate Netlist, and FPGA RTL to the synthesis and implementation team.
- Work on the setup and execution of Gate Level simulations.
- Demonstrate expertise in scripting languages, particularly Perl/Python, ensuring proficiency in a Linux computing environment.
- Utilize modeling skills with high-level transaction level modeling languages.
- Use AI/ML techniques to find corner case bugs and achieve coverage closure.
- BS/MS in EE/CE, plus 8+ years of Design Verification experience.
- Familiarity with ASIC, Computer, and Embedded Systems Architectures.
- Excellent oral and written communication skills with people at all levels, a must.
- Team player, with excellent debugging skills.
- Worked on the grounds-up development of verification infrastructure, test benches, and layered VIPs using System Verilog and UVM methodology.
- Demonstrated technical expertise in developing IP-level and system-level test plans, test bench development, functional coverage, stimulus generation, reference models, checkers, monitors, and scoreboards.
- Operated as a team player to coordinate team members and delivered on all aspects of SoC verification is a must.
- Good familiarity with all functional verification aspects such as regressions, code/functional coverage, and assertions.
- Good familiarity with SSD-related protocols such as PCIe/NVMe/SATA/SAS, NAND, and DDR.
- Good familiarity with Formal and PSS.
- Working experience with Verilog, System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement.
- Working experience with Design Verification Tools and Process flows with leading-edge ASIC technologies.
- Some familiarity with writing and debugging C tests for ARC/ARM processors.
- Scripting and test automation for regression.
- Experience with gate-level simulations.
Principal Engineer, ASIC Development Engineering - Bengaluru, India - Western Digital
Description
Company Description
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Job Description
Overview: The SoC Development team is actively seeking highly motivated engineers to join our experienced team working on the development of controller ESSD/CSSD SoCs.
Position: Verification Engineer - SoC Development Team
Responsibilities:
Qualifications
Education Requirements:
Skills/Experience:
Highly Desirable Experiences:
Additional Information
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