Lead DFT Engineer - Bangalore Urban, Karnataka

DFT Engineer · acl-digital is seeking a skilled DFT Engineer with 3+ years of experience in ASIC design and verification to implement and verify Design-for-Test methodologies. · Key Responsibilities: · Strong knowledge of DFT concepts is required. The ideal candidate should have ...

Purpose Of The Role · The Design for Testability (DFT) engineering organization at L&T Semiconductor Technologies (LTSCT) pioneers innovative methods and technologies in the areas of DFT architecture, verification, and post-silicon bring-up of state-of-the-art semiconductor chips ...

DFT engineer to develop methodologies and implement DFT for pre/post-silicon DFT flow contributing to SOC/Automotive/RISC-V product test quality. · ...

We are currently seeking a skilled DFT Engineer to join our team. · ...

We are looking for a DFT Engineer to join our dynamic team in Hyderabad and Banglaore. The successful candidate will have experience with industry-standard tools and flows for DFT architecture and methodologies for ASIC/SoC designs. · Develop and implement DFT architecture and me ...

DFT Engineer Role for ASIC design teams in Bangalore and Chennai. · ...

About the Role · As a DFT Engineer, you will be a key player in ensuring the reliability and manufacturability of our next-generation silicon. In 2026, the complexity of AI-driven chips requires advanced testability solutions. You will own the DFT flow from architecture to sign-o ...

We are having opportunities for DFT Engineers · Good exposer of complete DFT Cycles and able to work and debug independently · Very good experience on MBIST implementation, verification & debug with and without timing simulation. · ...

Location: Bangalore · Experience: Years  · Work Mode: 5 Days Work from Office · Mandatory Skills: Tessent, DFT, RTL insertion, Scan Insertion, ATPG, GLS, MBIST, pattern generation, validation, OCC, EDT, SSN, MBIST controller, IJTAG, IEEE 1600, Boundary scan, TCL, and debug · Job ...

Job summary · We are looking for SoC/ASIC Digital Design Engineer with experience in Design for Test (DFT). · ...

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scala ...

We are looking for a skilled Design for Test (DFT) Lead Engineer with experience in ASIC/SoC development to drive technical ownership of DFT implementation and mentoring junior engineers within fast-paced semiconductor projects. ...

We are seeking highly motivated DFT engineer to join a great team of engineering professionals involved in development validation delivery of high quality tests. · ...

DFT Engineer with 5+ years of experience in Chip level DFT and Post Silicon debug/analysis. Proficient in Python, PERL/Shell script and SDC constructs. · ...

Develop DFT architectures for complex SoC designs. · Drive scan insertion strategies. · Generate and analyze ATPG test patterns. · ...

Exciting Opportunity for · DFT Engineers · Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. · Role Description · Should have good post silicon DFT bring up and deb ...

We are looking for a DFT Engineer to work with cross‑functional teams on implementing and verifying advanced test features in complex IPs, subsystems, and SoCs. · Key Responsibilities: · • Implement DFT features including scan insertion, ATPG, memory BIST, IO BIST, and test acces ...

DFT Engineer with 5+ years of experience in Chip level DFT and Post Silicon debug / analysis. · ...

The Design for Testability (DFT) engineering for a leading Semiconductor company involves implementing various DFT techniques and conducting DFT simulations to ensure comprehensive test coverage. · ...

Architect implement and validate innovative DFT techniques on ARM SoCs inserting DFT logic into SoC style designs at the RTL level and at the Synthesis gate level validating all features and generating ATE targeted test patterns to be run on silicon. · ...

Larsen & Toubro DFT Engineer Job Description · Job Summary: · The Design for Testability (DFT) engineering organization at L&T Semiconductor Technologies pioneers innovative methods and technologies in semiconductor chips. · Responsibilities: · Implement various DFT techniques in ...