Clean Room Release Verification Engineer - Bengaluru, Hyderabad

Design and develop verification environments for complex digital designs using SystemVerilog, UVM. · ...

We are looking for an experienced Design Verification Engineer to join our high-performance VLSI/SoC verification team. · The ideal candidate will have strong expertise in SystemVerilog and UVM with hands-on experience verifying complex IPs and SoCs involving industry-standard pr ...

We are looking for seasoned Design Verification (DV) Engineers and Lead Architects to join our team in Bengaluru and Hyderabad. You will be responsible for the end-to-end verification of high-speed IPs and complex SoCs. · ...

Urgently looking for #PCIe Verification Engineer with experience in PCIe protocol & Design Verification. · 4+ years of experience. · ...

We are looking for an Embedded Software Engineer with 2-6 years of experience in embedded software testing, verification and validation. · Perform IV&V for embedded software components as per DO-178B/C standards. · Develop unit test plans test cases automated test scripts. · ...

Candidates with 1-3 Yrs expertise in SV UVM Verilog DV RTL design knowledge Preferred VLSI Diploma course mandatory. · ...

+SOC/IP Verification Engineer Role: SoC DV Engineer Key Highlights: · Extensive experience in fullchip SoC or subsystem verification · Strong handson experience in developing testbenches from scratch · Ability to derive detailed test plans from specifications · ...

+We are seeking an experienced Clean Room Release Verification Engineer to validate end-to-end product upgrades, deployment workflows, and integration flows for a complex, containerized product ecosystem running on Kubernetes (K8s) across cloud environments such as AWS EKS. · +Pe ...

The Design Verification Principal Engineer will contribute to processor-based SoCs in Automotive/Server/Video/5G product space with technically hands-on contributions and mentoring leadership roles. The role will involve working with stakeholders across geographies for SoC DV own ...

Senior design verification engineer responsible for functional verification of IPs and SoC using SystemVerilog and UVM. · ...

Mirafra Technologies is looking for experienced Design Verification Engineers to join our dynamic team in Hyderabad/Bangalore. · Develop and execute test plans and testbenches using SystemVerilog/UVM · Perform functional and code coverage analysis · Debug RTL and testbench issues ...

The ideal candidate will possess a problem-solving mindset, attention to detail and the curiosity to uncover hard to find issues. · ...

As a Technical Sales Engineer Embedded Software you ll be the bridge between GSAS s advanced embedded software solutions and the engineers building safety- and performance-critical systems. · ...

Mirafra is hiring experienced PCIE Verification Engineers for exciting opportunities with leading semiconductor clients in Hyderabad. · ...

Analog Layout Designer responsible for Design and development of critical analog, mixed-signal, custom digital block. · ...

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. · ...

This role is responsible for providing the Validation and Testing support. · ...

Layout design and verifications of GPIO library. · ...

+ Lead a team of physical design engineers to deliver high-quality results on time. · + Develop and maintain expertise in latest PDKs from Synopsys Custom Compiler. · 10-20 years of experience in Physical Design, Floor Planning, ICC, Timing Analysis, and Physical Verification usi ...

As an Analog Layout Design Engineer at Bengaluru/Hyderabad location you will work independently on block/IP levels analog layout design from schematic and ensure layout quality by applying principles of matching electromigration EM electrostatic discharge ESD latch-up prevention ...