Memory Layout - bangalore - Tech Mahindra

    Tech Mahindra
    Tech Mahindra bangalore

    8 hours ago

    tech mahindra background
    Description

    Job Description

    • Hands-on experience with the design and implementation of memory architectures, including control, sense amplifiers, I/O Blocks, bit cell arrays, decoders, and other critical components in a compiler framework.
    • Expertise in top-level memory integration and verification processes, including DRC (Design Rule Checking), LVS (Layout versus Schematic), density verification, and physical cleaning across the compiler space.
    • Strong understanding of IR/EM-related issues in memory layouts, ensuring optimal performance and functionality.
    • Mastery of cadence tools for layout design and Cadence/Mentor/Synopsys tools for physical verification checks, enabling efficient and accurate analysis.
    • Deep knowledge of ultra-deep sub-micron layout design challenges and adherence to DFM (Design for Manufacturing) guidelines.
    • Experience or strong interest in developing and optimizing memory compilers for high-performance applications.
    • Required experience level: 3-6 years
    • Technology nodes: TSMC 3nm and 5nm

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