Senior RTL Design Engineers - Bengaluru, India - Synopsys Inc

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    Engineering / Architecture
    • Senior RTL Design Engineer
    • Location: Bangalore
    • Experience: 4yrs to 10yrs
    • Work with Chip Architects to understand architecture and high-level product requirements.
    • Convert Chip Spec into RTL using internal IPs and external IPs.
    • Review Architecture and Design of custom IPs for integration into SOCs.
    • Design & Develop RTL for Interfaces, Power Management, Clocking, Reset, Test & Debug.
    • Develop and implement methodologies for I/O, DFT, Debug, Clocking and Power Management.
    • Provide technical leadership through lead by example, mentorship, and strong teamwork.
    • In this role, you work in a team developing SoCs. You will integrate industry standard and custom hardware IPs and subsystems into SoCs. You will work closely with System Architects, SoC architects, IP developers, and physical design teams to develop SoCs that meet the power, performance, and area goals. You will help define the processes, methods, and tools for the design and implementation of large complex SoCs. Develop chip-level and subsystem-level netlists integrating IPs and new designs

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    Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability.