STA Lead - Hyderabad, Telangana

Join AMD in providing innovative IP solutions as we embark on our journey into the cutting edge programmable logic based silicon designs by delivering the complex IP Solutions for multiple market segments. · ...

Technical Skills · Well versed with timing closure (STA), timing closure methodologies. · Pre/post-layout constraint development to timing closure. · Handshake with design team and develop functional/DFT constraints. · ID level constraint integration. · ​Multivoltage/switching aw ...

Lead full-chip and block-level timing signoff for complex SOC programs across advanced technology nodes. · ...

We are seeking an experienced Senior/Lead STA/Synthesis Engineer to join our team in Hyderabad. In this role you will be responsible for block/chip tile synthesis to achieve the best PPA and constraint generation and maintenance for block/soc for complex hierarchical designs. · - ...

As a Qualcomm Hardware Engineer you will plan design optimize verify and test electronic systems circuits mechanical systems Digital/Analog/RF/optical systems equipment and packaging test systems FPGA DSP systems that launch cutting-edge world class products. · ...

We are seeking a Principal Engineer – Implementation Lead to own synthesis and timing closure sign-off for low-power, chiplet-based MCU designs implemented on cost-optimized mature process nodes. · This role is critical for ensuring design quality and convergence while meeting po ...

We are seeking a Principal Engineer – Implementation Lead to own synthesis and timing closure sign-off for low-power, chiplet-based MCU designs implemented on cost-optimized mature process nodes. · This role is critical for ensuring design quality and convergence while meeting po ...

We are seeking a talented Implementation Engineer to join our dynamic team. · This is what you are responsible for : · - Synthesis and STA (static timing analysis).- Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL.- Pr ...

+Job summary · This role involves guiding a team of Physical Design Engineers analyzing calibre reports to ensure successful design project completion. · +ResponsibilitiesAnalyzing calibre reports. · ...

We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. · Performing static timing analysis (STA) for high-performance designs including DDR/L ...

We are seeking a highly motivated ASIC Physical Design Engineer to join our team. You will perform static timing analysis for high-performance designs including DDR/LPDDR architectures. · Performing static timing analysis (STA) for high-performance designs including DDR/LPDDR, · ...

As a Qualcomm Hardware Engineer you will plan design optimize verify and test electronic systems bringup yield circuits mechanical systems Digital Analog RF optical systems equipment and packaging test systems FPGA DSP systems that launch cuttingedge world class products. · ...

The Physical Verification (PV) Engineer is responsible for drive full-chip DRC/LVS signoff using ICV, debug and close DRC/LVS violations across block-level and hierarchical boundaries. · Execute ERC checks in process node 22nm or below · ...

We are looking for an experienced Physical Design Engineer – Lead to own and drive floorplanning and physical implementation for complex SoC and IP blocks from RTL to GDSII. · ...

Drive full-chip DRC/LVS signoff using ICV. Debug and close DRC/LVS violations across block-level and hierarchical boundaries. · ...

Renesas employs roughly 21,000 people in more than 30 countries worldwide. · ...

AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as Chiplet Interconnect IP (e.g UCIe), highly configurable high-speed memory, I/Os/PHYs to ...

We Are: · At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, · We offer a comprehensiv ...

This is a full-time position for a Design Verification Lead based in Hyderabad. · ...

A senior engineer with a minimum of three years of hands-on test development experience is required. The ideal candidate will have solid knowledge in defining test solutions for multi-million gate SOC and strong understanding of relationships between hardware, firmware and softwa ...