Principal ASIC/FPGA Design Verification Engineer responsible for developing testbench for constraint random environment, metric driven verification. · B.E./M.E. in ECE/Electronics or equivalent required. · 8-13 years of experience in RTL design verification for Block/IP/Sub-syste ...

You are an experienced and motivated FPGA Verification Team Lead joining the hardware engineering team. · ...

Meta is hiring ASIC Engineers within the Infrastructure organization to build and scale silicon for data center applications. · Work across all aspects of silicon lifecycle to deliver reliable and performant silicon solutions. · Create/develop validation plan, validation FW/SW, t ...

Meta is hiring ASIC Engineers within the Infrastructure organization. · ...

Meta is hiring ASIC Engineers within the Infrastructure organization. We are looking for individuals with experience in the FW Development/Pre/Post-Silicon Validation to build and scale silicon for data center applications. · ...

Meta is looking for ASIC Engineer to join our dynamic team and embark on a rewarding career journey. · ...

Senior ASIC Engineer (IP RTL design targeted for SOC Static checks some basic protocols) · ...

+Job summary · FPGA Engineer (Control Systems) to develop FPGA-based systems for controlling opto-electronic systems and performing real-time signal processing. · +Develop FPGA designs for real-time control of multiple opto-electronic systems and high-speed signal processing. · T ...

We help leading Consumer Products and Retail Services (CPRS) organizations unlock the value of technology and drive scalable, sustainable growth. · ...

We help leading Consumer Products and Retail Services (CPRS) organizations unlock the value of technology and drive scalable, sustainable growth. · ...

Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider enterprise networks and data centers with a ...

This is an opportunity to join HPE as an ASIC Engineer in Bangalore. The role involves designing high-performance blocks for networking ASICs. · ...

Digantara is redefining space safety and sustainability. · ...

This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. ...

The Common Hardware Group (CHG) delivers silicon optics and hardware platforms for Cisco's core Switching Routing and Wireless products. · Cisco Silicon One (#CiscoSiliconOne) enables customers to deploy best-of-breed silicon from Top of Rack (TOR) switches all the way through we ...

Digantara is building the world's first maps for space, Space-Mission Assurance Platform (Space-MAP). · ...

FPGA Engineer needed for developing FPGA-based systems for controlling opto-electronic systems and performing real-time signal processing. · ...

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. · Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ...

This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. · Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. · We help companies connect protect analyze and a ...

This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. · We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, · so they can turn insights ...

Develop algorithms for Next Generation High speed serial technologies using C#/MATLAB/C/C++. Implement and troubleshoot measurements/algorithms using DSP techniques for the customer problems and propose performance enhancements. · ...