Senior CPU and SoC RTL Engineer - Gandhinagar

We're hiring a Senior CPU & SoC RTL Engineer to join our growing team. · We're building the next generation of iRAM silicon and are looking for an experienced Hardware Engineer to make a real impact.Design and develop RTL using Verilog, SystemVerilog or Bluespec SystemVerilog. · ...

We are hiring RTL Design Engineer with experience of 4-8 years in Bangalore or Hyderabad. · ...

Design and develop FPGA modules using Verilog, work with Vivado for synthesis and implementation, and integrate peripherals. · ...

We are seeking an RTL Verification Engineer to join our team at Aerlync Labs. The successful candidate will be responsible for creating and implementing verification plans, writing test cases and ensuring the functional correctness of complex designs. · Creating and implementing ...

EngineerwouldbeinvolvedinthedigitaldesignofthenextgenerationPowermanagementmixedsignalproducts. · Developthedigitalcontrollersittingastruthheartofthechip. · DevelopperformanceenhancementalgorithmsforAnalogcircuitsanditsimplementationinRTL. · ...

This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products. · ...

We are seeking a highly skilled Physical Design Engineer with over 6 years of industry experience. The ideal candidate will have proven expertise as an individual contributor across multiple projects. · ...

The engineer would be involved in the digital design of next generation Power management mixed signal products. · ...

As a Physical Design Engineer/Lead in Ahmedabad, you will be responsible for implementing block level Physical Design from RTL to GDSII or Netlist to GDSII. · ...

Senior Physical Design Engineer will be responsible for floor-planning, timing constraints, physical synthesis etc. · Executing block level place and route assignments · ...

+This role will empower you to lead critical block or sub-system verification and full chip verification of complex Analog mixed signal products. · ...

We are seeking a highly skilled Emulation Engineer with strong experience in pre-silicon validation and hardware emulation platforms such as Palladium Protium Veloce Zebu or EP. · Work on emulation bring-up build flows and model compilation for large SoC or IP-level designs. · De ...

As a Physical Design Engineer at eInfochips (An Arrow Company), your role will involve the following responsibilities: Implementing block level Physical Design from RTL to GDSII or Netlist to GDSII. · ...

Lead the architecture design verification of digital blocks for mixed signal ASICs collaborate closely with Analog System teams to define specifications ensure seamless integration drive RTL design using Verilog/SystemVerilog optimize for power performance area follow digital des ...

We are seeking experienced Verification Engineers/Tech leads for Verification BU. · This role involves overseeing resource allocation, project coordination & development from scratch for IP/SoC verification. · ...

We are currently looking for DFT Engineers to join us at our Bangalore location. If you have 5+ years of experience in DFT (ASIC/SoC), this could be a great opportunity for you. · ...

We are seeking a Principal ASIC Design Engineer to lead the architecture, design, and verification of digital blocks for mixed-signal ASICs. · ...

We are seeking experienced Verification Engineers/Tech leads for Verification BU This role involves overseeing resource allocation project coordination & development from scratch for IP/SoC verification. · Oversight of resource allocation and project coordination. · Development f ...

The Associate Engineer will be responsible for principal accountabilities including floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization. · * Typically requires a 4 year degree and a minimum of 5 years of related experience; · * Inc ...

Principal Accountabilities Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing , extraction , timing closure , DFT , signal integrity and physical verification . Execute block level place and route assignme ...