DFT Lead - Bengaluru, Karnataka

We are seeking an experienced Design-for-Test (DFT) Lead to drive test strategy and execution for complex ASIC/SoC designs. · - Own and drive DFT architecture definition and implementation for IPs and SoCs · - Implement DFT features including JTAG / IEEE 1149.x scan chains , scan ...

We are seeking an experienced Design-for-Test (DFT) Lead with strong expertise in DFT architectures and implementation to drive test strategy and execution for complex ASIC/SoC designs. · ...

Weareseekingas skilledDesignforTest(DFT)Architect/Lead/Managerjoournoteam.ThisroleispivotalinensuringthetestabilityandmanufacturabilityofourASIC/SOCPproductsdesignedfortheautomotiveindustry. · ...

We are looking for a highly experienced DFT Engineer to lead and define Design-for-Test strategies for complex SoC designs. · ...

We are seeking an experienced Design-for-Test (DFT) Lead with strong expertise in DFT architectures and implementation to drive test strategy and execution for complex ASIC/SoC designs.The ideal candidate will have hands-on experience across the complete DFT flow, deep understand ...

We are seeking a skilled Design for Test (DFT) Architect/Lead/Manager to join our team. · ...

We're looking for an experienced DFT engineer skilled in full-chip DFT implementation and verification. · Hands-on with Scan Insertion, ATPG, JTAG, coverage analysis & DRC · Proficient in Verilog RTL, Spyglass, Tessent, Synopsys & Cadence tools · Experience in pattern simulation ...

Develop DFT strategy for hierarchical DFT, · scan, and Automatic Test Pattern Generation (ATPG). · Work with other Engineering teams to ensure that DFT Scan requirements are met and mutual dependencies are managed. · ...

Seeking an experienced DFT Lead Engineer to own and drive Design for Testability architecture. · ...

++The position requires an energetic, proactive, self-starting person,+who is able to lead and coordinate full chip DFT task+and work closely with other DFT engineers to explore new methodologies.+You must possess strong technical knowledge in the area of design-for-test (DFT).+ ...

The position requires an energetic proactive self-starting person who is able to lead and coordinate full chip DFT task and work closely with other DFT engineers to explore new methodologies. · Develop best in class highest quality DFT methodologies for all design teams in meetin ...

The SoC DFT Lead plays a critical role in delivering robust, testable, and manufacturable silicon. You will work on multiple advanced custom SoCs, collaborate with global teams and customers, · and help define DFT excellence and methodology for a rapidly scaling organization. · ...

A DFT lead engineer position in Greater Bengaluru Area requires 7+ years of experience in handling teams and proficiency with DFT tools. · ...

We are looking for an experienced DFT Lead Engineer to lead and execute Design-for-Test (DFT) activities for advanced ASIC/SoC projects. · The ideal candidate will own end-to-end DFT architecture, · drive high test coverage, · mentor junior engineers, · and collaborate closely wi ...

We are looking for an experienced DFT Lead Engineer to lead and execute Design-for-Test (DFT) activities for advanced ASIC/SoC projects.Lead and execute DFT activities for complex ASIC/SoC designs. · Determine the annual salary range based on the following information: · ...

We are looking for a · Lead DFT Engineer · to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. · ...

+DFT Lead Engineer position in a large design services organization with over 1000 employees. · +8-15 years of hands-on experience in DFT implementation and validation in the semiconductor industry. · +Responsibilities</h2,+ <ul type=none style= ...

The position requires an energetic proactive self- starting person who is able to lead and coordinate full chip DFT task and work closely with other DFT engineers to explore new methodologies. · ...

We are looking for an experienced DFT Lead Engineer to lead and execute Design-for-Test (DFT) activities for advanced ASIC/SoC projects. · ...

Develop DFT strategies for digital ICs. · Insert test structures such as scan chains. · Analyze coverage results of ATPG. · ...