Principal/ Master Design Engineer - Hyderabad, India - Axiado

    Axiado
    Axiado Hyderabad, India

    3 weeks ago

    Default job background
    Full time
    Description
    Job Description
    • Develop design and implementation of ARM based complex SoC's.
    • Micro architecture design, RTL implementation, verification, synthesis, timing closure of SoC and subsystems
    • Collaboration with Verification, Firmware, Software, FPGA, Systems, DFT, and Backend teams throughout various stages of chip development
    • Support test program development and post silicon validation.
    Qualifications
    • BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent with 15+ years of industry experience.
    • Experience of leading RTL design and verification teams for complex SoCs and ASIC products
    • In depth current knowledge in state of art tools required to build an optimized and configurable subsystem
    • Knowledge of RTL development using Verilog, System Verilog or VHDL
    • Exposure to all stages of design: initial concept, architecture specification, implementation, testing, documentation, and support
    • Expertise in writing efficient RTL code in Verilog and SoC integration.
    • Strong interpersonal and communication skills
    • Languages: Verilog, C/C++, Assembly language, Perl
    • Verification Languages such as System Verilog.
    • Strong understanding of CPU Architecture/micro-architectures.
    • Should have worked on interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.
    • Must have gone through at least one SoC tape out.
    • Should have Silicon bring-up and debug experience.
    • Should have team handling experience.

    "Good to Have" Skills and Experience

    • Proficient in writing clear, implementable micro-architecture specifications.
    • Hands on experience of working on ARM IPs based SoC.
    • Exposure to debugging RTL/ Netlist/ Gate Level simulations.
    • Exposure to UVM or other industry standard verification methodologies
    • Experience in design bring up and debug on FPGA based emulation platforms like HAPS, Veloce.

    Desirable Skills

    • Good in logical programming using C/C++
    • Familiar with verification process such as Test Plan development, Testcase development
    • Familiarity of Unix / Linux working environment
    Additional Information

    Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

    We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.

    Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.