asic verification engineer - Delhi - confidential

    confidential
    confidential Delhi

    4 days ago

    Full time Healthcare
    Description

    THE PERSON:

    • Creative innovator and thinker who loves technical problems and detail-oriented tasks
    • Exhibits relentless commitment to help the team meet quality and development goals on schedule with high quality
    • Drives to learn and perform at their highest potential in a technical capacity
    • Thrives in both a team environment and in individual contribution.
    • Able to lead a small team of engineers working towards a common objective
    • Able to learn independenly and acquire new skills required for the job
    • Communicates openly and clearly in meetings, presentations, emails, and reports

    KEY RESPONSIBILITIES:

    • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
    • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
    • Estimate the time required to write the new feature tests and any required changes to the test environment
    • Build the directed and random verification tests
    • Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
    • Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements

    PREFERRED EXPERIENCE:

    • Proficient in IP level ASIC verification
    • Proficient in debugging firmware and RTL code using simulation tools
    • Proficient in using UVM testbenches and working in Linux and Windows environment s
    • Experienced with Verilog, System Verilog, C, and C++
    • Experience with PCIe and/or Ethernet protocols
    • Developing UVM based verification frameworks and testbenches, processes and flows
    • Automating workflows in a distributed compute environment .
    • Exposure to simulation profile, efficiency improvement, acceleration
    • Good understanding and hands-on experience in the UVM concepts and System Verilog language
    • Scripting language experience: Python, Ruby, Makefile , shell preferred.
    • Exposure to leadership or mentorship is an asset
    • Desirable assets with prior exposure to network processors .

    ACADEMIC CREDENTIALS:

    • Bachelors or Masters degree in computer engineering/Electrical Engineering

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