No more applications are being accepted for this job
- Designing custom layout standardcell and memory layout as well as memory leafcell layout libraryfrom scratch including top levelintegration.
- Demonstrating good knowledge ofdifferent types of memory architectures and optimized layout designfor improved performance.
- Applying soundknowledge and handson experience in FinFET technology layout designand addressing design rule check (DRC)limitations.
- Proficiency in physicalverification flow and debug processes such as DRC LVS ERC andboundary conditions.
- Expertise in using CadenceVirtuoso layout editor and Calibre physical verificationflow.
- Relevant Bachelors or Mastersdegree in Electrical Engineering or a relatedfield.
- Proven experience in custom layoutstandard cell and memory layoutdesign.
- Demonstrated expertise in FinFETtechnology and layout design with a strong understanding of DRClimitations.
- Proficiency in utilizing CadenceVirtuoso layout editor and Calibre physical verificationflow.
- CustomLayout
- Standard Cell
- MemoryLayout Design
- FinFETTechnology
- Physical VerificationFlow
Memory Layout - Bengaluru, India - Hiringlabs Business Solutions
Description
CompanyOverview: Hiringlabs BusinessSolutions is a leading staffing and recruiting company thatspecializes in providing top talent to organizations across variousindustries.Role andResponsibilities: The MemoryLayout role involves the following responsibilities:
memory leafcell layout librarydesign,calibre,drc,physical verification flow,std celldesign,finfet technology,leafcell,custom layout,layout design,drclimitations,calibre physical verification flow,memory layoutdesign,memory architectures,memory layout,lvs,cadence virtuosolayout editor